SiGe pMOS Transistor Strain Management via Spacer Alignment
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Solution Overview
Problem
Existing processes for fabricating pMOS transistors on FDSOI substrates face issues such as lateral condensation of germanium beneath spacers and relaxation effects near trench isolations, leading to decreased performance due to excessive strain relaxation in the SiGe channel.
Innovation Solution
A process involving epitaxial growth of a pseudomorphic SiGe layer, followed by thermal oxidation to diffuse germanium into the silicon layer, forming a compressively strained SiGe channel aligned with spacers to avoid unwanted oxide formation beneath them, thereby maintaining strain and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a condensation step is implemented to diffuse germanium from the SiGe layer into the silicon layer, then a compressively strained SiGe channel is formed, but lateral condensation occurs beneath the spacers causing unwanted oxide formation and performance degradation
Solution Approach 1:
The patent removes the SiGe layer laterally beneath the spacers before performing the condensation step. This extraction of the problematic SiGe material prevents germanium from diffusing laterally under the spacers during thermal oxidation, eliminating the source of unwanted oxide formation while preserving the SiGe layer in the active channel region where strain is needed.
Solution Approach 2:
The patent performs a preliminary lateral removal of the SiGe layer beneath the spacers before the condensation step. This preliminary action prevents the harmful lateral condensation from occurring in the first place, rather than attempting to correct it afterward. The removal is done selectively to maintain SiGe in the active regions while clearing it from beneath the spacers.
2Reliability
If trench isolations are formed to separate nMOS and pMOS zones, then device isolation is achieved, but relaxation effects occur near the trench isolations causing excessive strain relaxation in the SiGe channel
Solution Approach 1:
The patent applies different treatments to different regions: the SiGe layer is removed laterally beneath the spacers in the isolation regions while being preserved in the active channel regions. This local differentiation allows trench isolations to provide proper device isolation while preventing strain relaxation in the active SiGe channels, as the condensation process only occurs where SiGe is present.
3Stress or pressure
If the SiGe layer is deposited thick enough to provide sufficient compressive strain, then strain magnitude is adequate, but the layer becomes prone to relaxation effects
Solution Approach 1:
The patent deposits a SiGe layer with thickness and germanium content that would normally exceed the critical thickness for relaxation, but then selectively removes portions of it laterally beneath the spacers. This partial removal strategy allows the active channel regions to retain sufficient thickness for adequate strain while preventing relaxation by removing material from regions where it would cause problems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains compressive strain in the SiGe channel, enhancing the performance of pMOS transistors by preventing strain relaxation and maintaining uniform germanium concentration, thus improving electron mobility.
Implementation Method 1
A process of condensation of the germanium into the silicon layer by thermal oxidation is next implemented. A thermal-oxidation operation is implemented, resulting in the formation of a layer of SiO2 in the upper portion and diffusing the germanium into the silicon layer
Implementation Method 2
diffusing the germanium into the silicon layer to transform it into a layer of SiGe
Implementation Method 3
raised source and drain are deposited by epitaxy of silicon on top of the layer of SiGe
Data Source
AI summary
A process for fabricating a field-effect transistor includes providing a structure including a first silicon layer and a second layer, made of SiGe alloy, covering the first silicon layer. The method further includes forming a sacrificial gate covered with a hardmask on top of the second layer made of SiGe alloy and etching the second layer made of SiGe alloy, following the pattern of the hardmask in order to delimit an element made of SiGe alloy in the second layer. The method also includes forming spacers on top of the first silicon layer on either side of the sacrificial gate and of the element, removing the sacrificial gate, and enriching the first layer arranged beneath the element in germanium using a germanium condensation process.