FinFET SiGe-Si Alternating Fin Structure for Electrical Performance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved electrical characteristics, particularly in down-scaled FinFET structures, where the scaling of integrated circuit density and high operating speed with accuracy are hindered by limitations in transistor structure optimization.
Innovation Solution
A semiconductor device design featuring a fin structure with alternately stacked silicon germanium (SiGe) and silicon (Si) patterns, where the germanium content in SiGe patterns increases towards the center, and a gate electrode and insulating film configuration that enhances electrical performance by minimizing band gap discontinuity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET structure is down-scaled to improve integration density, then integration density is improved, but electrical characteristics and operating accuracy deteriorate
Solution Approach 1:
The patent applies local quality by creating alternating Si/SiGe fin patterns where different material compositions are positioned at specific locations. The SiGe layers with higher germanium content (30-70%) are placed in alternating fins to provide localized strain enhancement, while Si layers maintain baseline electrical properties. This spatial variation in material composition allows the structure to maintain good electrical characteristics despite down-scaling, as the strained SiGe regions improve carrier mobility without requiring overall device enlargement.
Solution Approach 2:
The patent employs composite materials by combining silicon (Si) and silicon germanium (SiGe) in alternating fin structures. This composite approach leverages the beneficial properties of both materials: Si provides stable electrical characteristics and成熟的工艺 compatibility, while SiGe introduces mechanical strain to enhance carrier mobility. The alternating stack creates a composite fin structure that achieves both high integration density through scaling and maintained electrical performance through material diversity.
2Reliability
If alternating Si and SiGe fin patterns are used to improve carrier mobility through strain, then carrier mobility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the fin structure into alternating Si and SiGe segments rather than using a single material throughout. This segmentation allows strain to be introduced in discrete, controlled portions of the channel, improving carrier mobility where needed. The segmented approach also simplifies manufacturing compared to continuous SiGe layers, as it can be achieved through sequential epitaxial growth or selective deposition techniques that are extensions of existing processes.
Solution Approach 2:
The patent utilizes parameter changes by varying the germanium content in SiGe layers (30-70% Ge) and controlling layer thicknesses (5-50 nm) to optimize strain effects. By adjusting these material parameters, the patent achieves desirable carrier mobility enhancement without requiring complex device geometries or additional processing steps. The parameter optimization allows standard manufacturing techniques to produce the strained structure with controlled complexity.
3Reliability
If germanium content in SiGe patterns is increased to enhance electrical performance, then electrical characteristics are improved, but material quality control becomes more difficult
Solution Approach 1:
The patent applies parameter changes by specifying a germanium content range (30-70%) rather than a single fixed value, providing flexibility in manufacturing while ensuring performance targets are met. This range-based approach acknowledges variations in deposition processes and allows optimization based on specific fabrication capabilities. The patent also controls layer thickness parameters (5-50 nm) to maintain strain effects even when germanium content varies within the specified range, thereby managing material quality control challenges.
Solution Approach 2:
The patent uses composite materials (Si and SiGe alternation) to provide a buffer against germanium content variations. The Si layers act as reference regions with stable, well-controlled properties, while the SiGe layers provide strain enhancement. This composite structure allows the overall device performance to remain robust even when germanium content in SiGe layers varies within the specified range, as the alternating Si regions maintain electrical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves electrical characteristics by maintaining performance across the channel structure, preventing performance deterioration due to band gap discontinuity and enabling higher voltage operation in peripheral circuit regions.
Implementation Method 1
Each of the plurality of first semiconductor patterns may have a first germanium (Ge) content gradient that increases toward a first center thereof in a vertical thickness direction thereof. A first Ge content in the first center of each of the first semiconductor patterns may be in a first range of 25% to 35%.
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).