SiGe and Silicon Fin Formation on Oxide via Thermal Oxidation
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Solution Overview
Problem
In semiconductor processing, the use of thick silicon-on-insulator (SOI) substrates can lead to Ge diffusion into N-type field effect transistor (NFET) areas, degrading performance and causing leakage, while fin corners are susceptible to etching before SiGe growth, resulting in suboptimal finFET device performance.
Innovation Solution
A method involving growing a SiGe layer followed by a silicon layer on a bulk Si substrate, patterning fin structures, forming trenches, selectively etching the SiGe layer to create voids, and thermally oxidizing the SiGe layer to drive Ge into the silicon layer, forming SiGe fins on an oxide layer for P-type field effect transistors and silicon fins on a dielectric material for N-type transistors, thereby isolating fins from the substrate and preventing Ge diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick SOI substrates are used to form fins, then fin structures can be formed, but Ge diffuses into NFET areas degrading performance and causing leakage
Solution Approach 1:
The substrate is segmented into separate regions: NFET regions with silicon fins on oxide, and PFET regions with SiGe fins on oxide. This spatial segmentation prevents Ge diffusion into NFET areas while maintaining fin structure formation in both regions.
Solution Approach 2:
Different materials are used in different locations: silicon is used in NFET regions to prevent Ge diffusion, while SiGe is used in PFET regions to enhance hole mobility. The oxide layer is locally positioned under NFET fins to prevent substrate leakage.
2Reliability
If SiGe layer is grown before fin patterning, then channel mobility in PFETs is enhanced, but fin corners are susceptible to etching before SiGe growth
Solution Approach 1:
The SiGe layer is grown in advance before fin patterning, ensuring that the material is already in place to enhance PFET channel mobility. The fin patterning process then selectively etches through the SiGe and silicon layers to form precise fin structures with protected corners.
Solution Approach 2:
The process transitions from planar layer growth to three-dimensional fin structures through controlled etching. The fin corners are protected during this transition by the sequential etching of dielectric layers and the selective removal of materials, maintaining integrity while achieving vertical structures.
3Reliability
If SOI substrate is used, then fin structures are formed, but leakage to base substrate occurs
Solution Approach 1:
An oxide layer is introduced as an intermediary between the silicon fins and the substrate in NFET regions. This oxide layer acts as an electrical isolator, preventing leakage to the base substrate while allowing the fin structures to be properly formed.
4Object-generated harmful factors
If selective etching is performed to remove SiGe from NFET regions, then Ge diffusion is prevented, but process complexity increases
Solution Approach 1:
Different etching conditions are applied to different regions: NFET regions undergo selective etching to remove SiGe and prevent Ge diffusion, while PFET regions retain SiGe for enhanced mobility. This localized approach targets Ge diffusion prevention only where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves PFET performance by enhancing channel mobility, reduces source-to-drain punch-through leakage, and maintains wafer commonality across devices by isolating fins with a dielectric layer, addressing issues of Ge diffusion and fin corner etching in existing processes.
Implementation Method 1
thermally oxidizing the SiGe layer to drive Ge into the silicon layer
Implementation Method 2
drive Ge into the silicon layer to form SiGe fins
Data Source
AI summary
A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.