SiGe Source/Drain EPI Structure for Lower Contact Resistance
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to increased source/drain contact resistance, which is a significant challenge in reducing overall transistor resistance.
Innovation Solution
The formation of source/drain features with heavy p-type doping, particularly at the upper portion, using multiple epitaxially grown layers of silicon germanium with varying boron doping concentrations, including a sub-layer with the highest doping at the corners and top, to reduce series and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then productivity and production efficiency are improved, but source/drain contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain structure where different layers have different doping concentrations. Specifically, the first source/drain layer has a first doping concentration while the second source/drain layer has a second doping concentration that is higher than the first. This non-uniform doping distribution locally optimizes the contact regions to reduce contact resistance while maintaining the scaled-down geometry for high functional density.
Solution Approach 2:
The patent employs composite materials by forming a multi-layer source/drain structure comprising different semiconductor layers with distinct electrical properties. The combination of a lightly-doped first source/drain layer and a heavily-doped second source/drain layer creates a composite structure that simultaneously achieves low contact resistance and compatibility with scaled device dimensions.
2Reliability
If source/drain contact resistance is reduced through heavy doping, then overall transistor resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the source/drain region into multiple discrete layers - a first source/drain layer and a second source/drain layer - rather than using a single uniform layer. This segmentation allows each layer to be independently doped at different concentrations, with the second layer providing heavy doping for low contact resistance while the first layer maintains structural integrity, thereby managing manufacturing complexity through modular construction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces series resistance and contact resistance, maintaining the structural integrity of the source/drain features during processing and enhancing the performance of semiconductor devices.
Implementation Method 1
epitaxially growing a first semiconductor layer having silicon germanium in the source/drain trench; epitaxially growing a second semiconductor layer having silicon germanium above the first semiconductor layer
Data Source
AI summary
A method includes providing a substrate, a semiconductor fin extending from the substrate, and a gate structure over the substrate and engaging the semiconductor fin; etching the semiconductor fin to form a trench; and epitaxially growing a semiconductor structure in the trench, which includes epitaxially growing a first semiconductor layer having silicon germanium (SiGe); epitaxially growing a second semiconductor layer having SiGe above the first semiconductor layer; epitaxially growing a third semiconductor layer having SiGe over the second semiconductor layer; and epitaxially growing a fourth semiconductor layer having SiGe and disposed at a corner portion of the semiconductor structure. Each of the first, second, third, and fourth semiconductor layers includes a p-type dopant, and the fourth semiconductor layer has a higher dopant concentration of the p-type dopant than each of the first, second, and third semiconductor layers.


