SiGe Source/Drain Strain Engineering for Transistor Performance
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Solution Overview
Problem
In semiconductor devices, particularly at the 90 nm node and finer, it is challenging to improve transistor performance due to increased standby off-leak current, which hinders the enhancement of current drive capability, and existing strained silicon techniques have limitations in effectively enhancing carrier mobility and transistor speed.
Innovation Solution
A semiconductor device structure is introduced, featuring a p-channel MOS transistor with a gate electrode, a SiGe layer embedded in the source/drain region, comprising a first SiGe layer with a lower Ge composition ratio, an intermediate layer, a second SiGe layer with a higher Ge composition ratio, and a side wall structure that applies compressive stress to the channel region, optimizing strain distribution to enhance carrier mobility and transistor speed while preventing dislocation and roll-off characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate length of transistor is reduced to improve microminiaturization, then the transistor size is reduced, but the standby off-leak current is increased and current drive capability deteriorates
Solution Approach 1:
The patent applies different Ge composition ratios at different locations within the source/drain region. The first SiGe layer has a lower Ge composition ratio (5-20%) while the second SiGe layer has a higher Ge composition ratio (20-40%), creating localized strain optimization that improves carrier mobility without increasing off-leak current
Solution Approach 2:
The patent uses a composite structure consisting of multiple SiGe layers with different Ge composition ratios embedded in the source/drain region. This composite material approach allows simultaneous optimization of strain distribution and electrical characteristics, resolving the contradiction between miniaturization and performance
2Ease of manufacture
If a single-layer SiGe structure is used to apply compressive stress to the channel region, then the manufacturing process is simple, but the strain distribution is insufficient to effectively enhance carrier mobility
Solution Approach 1:
The patent divides the SiGe layer into multiple segments with different Ge composition ratios. The first SiGe layer (lower Ge content) and second SiGe layer (higher Ge content) are formed as separate layers, allowing independent optimization of strain distribution to effectively enhance carrier mobility
3Speed
If the Ge composition ratio is increased to enhance compressive stress and carrier mobility, then the transistor speed is improved, but dislocation and roll-off characteristics occur
Solution Approach 1:
The patent applies higher Ge composition ratio (20-40%) only in the second SiGe layer adjacent to the channel region where maximum strain is needed, while the first SiGe layer has lower Ge composition ratio (5-20%). This localized high-strain approach improves carrier mobility and transistor speed without excessive Ge content that would cause dislocation
Solution Approach 2:
The patent optimizes the Ge composition ratio parameters within specific ranges (first layer: 5-20%, second layer: 20-40%) to achieve the optimal balance between compressive stress magnitude and crystal structure stability, preventing dislocation while maximizing carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure significantly increases compressive stress in the channel length direction, improving transistor current drive capability and operating speed while maintaining sufficient roll-off characteristics by carefully controlling Ge mole fractions and film thicknesses, thereby enhancing the performance of ultrafine semiconductor devices.
Implementation Method 1
Since SiGe has a lattice constant larger than that of silicon, a crystal of a SiGe layer is, in a sense, forcibly lattice-matched with a silicon substrate in the substrate in-plane direction. Thereby, the silicon substrate is expanded in the direction perpendicular to the substrate. As a result, a compressive strain is introduced into the channel region in the substrate in-plane direction
Implementation Method 2
a SiGe layer is embedded into the recessed portion by an epitaxial method
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.