Silicon-Germanium Source/Drain Transistor Contact Resistance

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Solution Overview

Problem

The reduction in size and operating speeds of transistors in semiconductor devices leads to decreased turn-on current and increased contact resistance, reducing the overall operating speed of semiconductor devices.

Innovation Solution

A semiconductor device is formed with a source/drain pattern of silicon-germanium doped with dopants, a metal germanosilicide layer is created by reacting a metal layer with a capping layer of silicon-germanium, where the germanium proportion in the capping layer is lower than in the source/drain pattern, to enhance carrier mobility and reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor size is reduced to increase integration, then device density is improved, but turn-on current decreases and contact resistance increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidtransistor operating speed
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material composition parameter by forming source/drain regions with silicon-germanium alloy having different germanium concentrations. The channel region maintains low germanium content for high carrier mobility, while source/drain regions have higher germanium content to reduce contact resistance and improve turn-on current, thus resolving the contradiction between integration density and operating speed.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by creating non-uniform germanium distribution throughout the transistor structure. Specifically, the source and drain regions are doped with higher germanium concentration locally, while the channel region maintains lower germanium concentration. This localized material property variation simultaneously improves contact resistance at source/drain interfaces and preserves carrier mobility in the channel, addressing the technical contradiction.

Inventive Principle:
Principle #3Local quality

2Productivity

If transistor size is reduced, then integration scale is improved, but contact resistance between drain/source region and contact structure increases

Engineering Contradiction:
Improveintegration scaleVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent modifies the material composition parameter by incorporating silicon-germanium alloy with optimized germanium concentration in source/drain regions. This parameter change reduces contact resistance by improving material properties at the contact interface, allowing higher integration scales without suffering from increased contact resistance.

Inventive Principle:
Principle #35Parameter changes

3Speed

If turn-on current is increased to improve operating speed, then operating speed is improved, but device size increases

Engineering Contradiction:
Improvetransistor operating speedVSAvoidtransistor size
Core Design Contradiction:
SpeedVSVolume of moving object

Solution Approach 1:

The patent changes the material composition parameter by using silicon-germanium alloy with controlled germanium concentration in source/drain regions. This enables increased turn-on current and improved operating speed without proportionally increasing device size, as the material property optimization allows for more efficient current flow within the same footprint.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution increases the operating speed of transistors by improving carrier mobility and reducing contact resistance, while also enhancing production yield and preventing metal penetration into the channel region.

Implementation Method 1

forming a metal layer on the capping layer and reacting the metal layer with the capping layer by performing an annealing process to form a metal germanosilicide layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

reacting the metal layer with the capping layer by performing an annealing process to form a metal germanosilicide layer

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 3

forming a source/drain pattern of silicon-germanium doped with dopants to fill the recess region

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS8338261B2Semiconductor device including field effect transistor and method of forming the same
Publication Date: 2012.12.25 SAMSUNG ELECTRONICS CO LTD
  • US8338261B2 patent drawing
  • US8338261B2 patent drawing
  • US8338261B2 patent drawing

AI summary

A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.