SiGe Stack Composition for Selective Etching in Semiconductor Structures

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Solution Overview

Problem

Existing etching processes for SiGe stacks in semiconductor fabrication face challenges in selectively removing the SiGe layer with high germanium concentration, leading to undesired material loss in Si layers due to high inter-diffusion, while those with low germanium concentration are not effectively etched due to low selectivity.

Innovation Solution

A SiGe stack with varying germanium concentrations is employed, where the middle layer has the highest concentration, allowing for controlled etching rates, facilitating the removal of the SiGe layer while minimizing Si layer loss, by adjusting thickness and germanium concentration of each layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of substance

If etching process is used to remove SiGe layer with low germanium concentration, then Si layer protection is improved, but SiGe layer removal efficiency decreases due to low selectivity

Engineering Contradiction:
ImproveSi layer material lossVSAvoidSiGe layer removal efficiency
Core Design Contradiction:
Loss of substanceVSProductivity

Solution Approach 1:

The SiGe layer is segmented into two functional parts: a first SiGe layer with lower germanium concentration that provides protection during etching, and a second SiGe layer with higher germanium concentration that ensures effective removal. This segmentation allows each layer to fulfill its specific role in resolving the contradiction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The germanium concentration is locally optimized for each SiGe layer based on its position and function. The first SiGe layer (adjacent to Si) has lower Ge concentration (30-40%) to minimize inter-diffusion, while the second SiGe layer (exposed to etchant) has higher Ge concentration (40-50%) for etching selectivity and removal efficiency.

Inventive Principle:
Principle #3Local quality

2Reliability

If germanium concentration is increased in SiGe layer, then etching selectivity is improved, but inter-diffusion between Si and SiGe layers increases causing material loss

Engineering Contradiction:
Improveetching selectivityVSAvoidSi layer material loss
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The SiGe structure is segmented into two layers with different germanium concentrations. The first SiGe layer has lower Ge concentration to minimize inter-diffusion with Si, while the second SiGe layer has higher Ge concentration to provide etching selectivity. This segmentation allows both requirements to be satisfied simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Germanium concentration is locally optimized: the first SiGe layer (in contact with Si) has lower Ge concentration (30-40%) to reduce inter-diffusion, while the second SiGe layer (exposed to etchant) has higher Ge concentration (40-50%) to enhance etching selectivity. Each layer's composition is tailored to its specific functional requirement.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables effective removal of the SiGe layer with reduced material loss in Si layers, improving etching efficiency and facilitating subsequent fabrication steps.

Implementation Method 1

Existing etching processes for SiGe stacks in semiconductor fabrication face challenges in selectively removing the SiGe layer with high germanium concentration

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

leading to undesired material loss in Si layers due to high inter-diffusion

Methodology Applied
Scientific EffectInter-diffusion: Diffusion

Data Source

PatentUS12453147B2Semiconductor structure and method of fabricating the semiconductor structure
Publication Date: 2025.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12453147B2 patent drawing
  • US12453147B2 patent drawing
  • US12453147B2 patent drawing

AI summary

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.