SiGe Strain-Inducing Layer Formation at Replacement Poly Gate Stage
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Solution Overview
Problem
In semiconductor manufacturing, the strain-inducing SiGe layer in fin field-effect transistors (finFETs) experiences stress relaxation due to sequential processes and thermal steps, limiting Ge concentration and doping flexibility, which affects carrier confinement and device performance.
Innovation Solution
Forming a SiGe strain-inducing layer or cap layer at the replacement polysilicon gate (RPG) stage after high-temperature processes, allowing higher Ge concentration and greater doping flexibility, and using techniques like tilt implantation and dual capping layers to enhance carrier confinement and prevent metal migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential processes and thermal steps are used in finFET manufacturing, then device fabrication is completed, but stress relaxation occurs in the SiGe strain-inducing layer limiting Ge concentration
Solution Approach 1:
The SiGe strain-inducing layer is formed at the replacement polysilicon gate (RPG) stage after high-temperature processes are completed. By performing the strain layer formation as a preliminary action after thermal processing, the layer is exposed to minimal subsequent thermal stress, preventing stress relaxation and maintaining high Ge concentration for enhanced carrier confinement and device performance
Solution Approach 2:
The patent changes the timing parameter of SiGe layer formation from early process stages to the RPG stage. This parameter change allows the layer to withstand high-temperature processes without experiencing stress relaxation, thereby maintaining stable Ge concentration and improving device performance
2Reliability
If higher Ge concentration is used in SiGe layer, then carrier confinement is improved, but stress relaxation increases limiting doping flexibility
Solution Approach 1:
The SiGe layer is formed after high-temperature processes at the RPG stage, which is a preliminary action that prevents subsequent thermal stress. This timing allows higher Ge concentration to be maintained without stress relaxation, thereby improving carrier confinement while preserving doping flexibility for optimized device performance
Solution Approach 2:
The patent applies local quality by forming the SiGe strain-inducing layer with specific high Ge concentration at the channel region where carrier confinement is most critical. The layer is deposited selectively at the RPG stage, providing localized strain enhancement exactly where needed while maintaining overall doping flexibility
3Reliability
If tilt implantation and dual capping layers are used, then carrier confinement and metal migration prevention are improved, but process complexity increases
Solution Approach 1:
The patent merges tilt implantation and dual capping layer formation into the RPG stage process flow. By combining these techniques at a single process stage, the patent achieves improved carrier confinement and metal migration prevention while minimizing the increase in overall process complexity compared to implementing these as separate sequential steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains higher Ge concentration and doping flexibility, improving carrier confinement and reducing external resistance, thereby enhancing finFET performance and preventing metal migration during elevated temperature operations.
Implementation Method 1
Strain engineering is employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
Implementation Method 2
using techniques like tilt implantation and dual capping layers to enhance carrier confinement and prevent metal migration
Data Source
AI summary
The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.