SiGe Strained pMISFET Regions for Drivability and Reliability
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Solution Overview
Problem
Conventional methods for enhancing mobility in semiconductor devices by embedding silicon germanium (SiGe) in source/drain regions face challenges in achieving both high drivability and reliability due to increased crystal defects at higher Ge concentrations, making it difficult to form pMISFETs with both high performance and reliability in a single chip.
Innovation Solution
The solution involves forming first and second pMISFET regions with SiGe layers of different Ge concentrations to apply distinct compression strains to their respective Si channels, allowing for the formation of high-drivability and high-reliability transistors on the same chip by varying the Ge concentration and recess depths in the SiGe layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Ge concentration in the SiGe layer is increased to enhance mobility and drivability, then the compression strain on the Si channel increases and mobility is enhanced, but the risk of crystal defects increases and reliability deteriorates
Solution Approach 1:
The patent applies different Ge concentrations in SiGe layers to different pMISFET regions (first pMISFET region uses higher Ge concentration for high drivability, second pMISFET region uses lower Ge concentration for high reliability). This local differentiation allows each region to be optimized for its specific function, resolving the contradiction between drivability and reliability by making quality non-uniform across the device structure.
Solution Approach 2:
The semiconductor device is segmented into multiple pMISFET regions with distinct SiGe layer configurations. The first pMISFET region and second pMISFET region are separated and independently optimized, allowing the system to simultaneously achieve high drivability in one segment and high reliability in another segment without compromise.
2Productivity
If the Ge concentration in the SiGe layer is made higher to achieve high drivability, then mobility is enhanced, but both high drivability and high reliability cannot be attained together in one chip
Solution Approach 1:
Different regions of the chip are assigned different Ge concentrations based on their functional requirements. The first pMISFET region uses higher Ge concentration (e.g., 10-30%) to maximize drivability for performance-critical circuits, while the second pMISFET region uses lower Ge concentration (e.g., 0-20%) to ensure reliability for stability-critical circuits, allowing both qualities to coexist in the same chip.
Solution Approach 2:
The chip is divided into functionally distinct pMISFET regions that can be independently optimized. This segmentation enables simultaneous fabrication of high-drivability transistors and high-reliability transistors on a single chip by assigning appropriate SiGe layer parameters to each region during the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of pMISFETs with high drivability and reliability by optimizing the Ge concentration and strain levels in the SiGe layers, enhancing the overall quality of CMOS transistors while minimizing the risk of crystal defects.
Implementation Method 1
first SiGe layers which apply first compression strain to the first Si channel being embedded and formed in the first pMISFET region to sandwich the first Si channel
Implementation Method 2
embedding silicon germanium (SiGe) in source/drain regions of MISFETs and straining Si channels
Data Source
AI summary
A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.