Nanostructured Channel Layers With SiGe Stress for P-Type GAA FETs
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, necessitating improved nanostructured channel structures for enhanced performance and efficiency.
Innovation Solution
Incorporation of a silicon-germanium (SiGe) doped region and a capping layer in the nanostructured channel layer of FETs, such as GAA FETs, to induce compressive stress, enhancing carrier mobility and ON current in p-type FETs, while maintaining a controlled spacing between adjacent nanostructured channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then higher performance and lower costs are achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by introducing SiGe doped regions specifically in the channel layer of p-type FETs, while n-type FETs use different channel structures. This localized differentiation allows optimization of carrier mobility in p-type devices without complicating the overall manufacturing process, as the doping is confined to specific regions rather than applied uniformly across all devices.
Solution Approach 2:
The patent utilizes parameter changes by varying the germanium concentration in SiGe layers to control compressive stress levels in the channel. By adjusting the Ge concentration parameter, the manufacturing process can optimize carrier mobility without fundamentally changing the device architecture or manufacturing flow, thus improving performance while maintaining process simplicity.
2Reliability
If SiGe doped region and capping layer are incorporated to induce compressive stress, then carrier mobility and ON current are enhanced, but device structure complexity increases
Solution Approach 1:
The patent applies the nested doll principle by placing the SiGe doped region within the channel layer, which is itself surrounded by a capping layer, all contained within the FET structure. This nested arrangement allows multiple functional layers to be integrated without significantly increasing lateral footprint or manufacturing steps, as each layer is deposited or formed in sequence within the same device footprint.
Solution Approach 2:
The patent uses composite materials by combining silicon and germanium to form SiGe alloys with specific compositional gradients. This composite approach enables tuning of material properties (compressive stress, carrier mobility) while maintaining structural integrity, avoiding the need for separate discrete stress-inducing components that would increase device complexity.
3Reliability
If spacing between adjacent nanostructured channel layers is controlled, then threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers or using self-aligned deposition techniques before final channel layer formation. These preliminary structures guide the positioning of subsequent layers, ensuring controlled spacing without requiring high-precision alignment steps during critical channel formation, thus reducing manufacturing precision requirements while maintaining threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SiGe doped region and capping layer improve the performance of p-type FETs by increasing carrier mobility and ON current, providing better threshold voltage control in scaled-down devices.
Implementation Method 1
Incorporation of a silicon-germanium (SiGe) doped region and a capping layer in the nanostructured channel layer of FETs, such as GAA FETs, to induce compressive stress, enhancing carrier mobility and ON current in p-type FETs
Data Source
AI summary
The present disclosure provides nanostructured channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with a first nanostructured layer and a second nanostructured layer on a fin base, forming a polysilicon structure on the superlattice structure, removing the second nanostructured layer to form a first gate opening, removing the polysilicon structure to form a second gate opening, forming a capping layer on the first nanostructured layer, modifying the first nanostructured layer to form a nanostructured channel layer having an undoped semiconductor region and a doped semiconductor region surrounding the undoped semiconductor region, and forming a gate structure in the first and second gate openings and surrounding the nanostructured channel layer.