SiGe Stressor Uniformity via Selective Etch-Back
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Solution Overview
Problem
The existing methods for forming PMOS devices with SiGe stressors suffer from pattern-loading effects, leading to non-uniform film thickness and composition due to differences in local pattern density, which affects device performance and is difficult to control.
Innovation Solution
A method involving the formation of gate dielectrics, gate electrodes, spacers, and recesses in semiconductor substrates, followed by selective epitaxial growth of SiGe stressors, and an etch-back process to adjust thickness uniformity, with different etching rates for dense and isolated regions, and the use of passivation materials to enhance etching differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is used to form SiGe stressors, then compressive stress is applied to improve PMOS device performance, but pattern-loading effects cause non-uniform film thickness and composition
Solution Approach 1:
The patent applies different etching conditions to different regions of the wafer based on pattern density. Isolated regions receive etching treatment while dense regions are protected by passivation, creating locally differentiated processing that compensates for the non-uniform epitaxial growth caused by pattern-loading effects.
Solution Approach 2:
The patent applies passivation materials to dense regions before the etching step to prevent etching in those areas. This preliminary protective action counteracts the tendency for over-etching in dense regions, ensuring uniform final thickness across the wafer despite initial growth non-uniformity.
2Manufacturing precision
If dummy patterns are added to sparse regions, then pattern density uniformity is improved and pattern-loading effects are reduced, but additional process steps and costs are incurred
Solution Approach 1:
The patent changes the processing parameters (etching vs. passivation) based on the existing pattern density distribution across the wafer. Instead of modifying the layout with dummy patterns, the method uses parameter differentiation during etching to achieve uniform results, avoiding additional fabrication steps.
Solution Approach 2:
Instead of adding material (dummy patterns) to sparse regions to equalize density, the patent removes material (etches) selectively from isolated regions. This inverse approach achieves the same goal of uniformity by compensating for growth differences through selective removal rather than addition.
3Manufacturing precision
If epitaxy parameters are adjusted to reduce pattern-loading effects, then film uniformity may be improved, but other epitaxy properties such as composition are also impacted
Solution Approach 1:
The patent segments the wafer into dense and isolated regions and applies different post-growth treatments to each segment. By separating the processing into region-specific steps (passivation for dense regions, etching for isolated regions), the method corrects thickness non-uniformity without requiring global changes to epitaxy parameters that would affect composition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves more uniform SiGe stressor formation, adjustable facets, and minimal additional cost, effectively reducing pattern-loading effects and improving device performance by ensuring consistent thickness and composition across the wafer.
Implementation Method 1
epitaxially growing SiGe stressors in the recesses and annealing
Implementation Method 2
Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region
Implementation Method 3
different etching rates for dense and isolated regions, and the use of passivation materials to enhance etching differences
Data Source
AI summary
A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.