Single-Crystal Silicon Superlattice Bonding for Low-Leakage 3D Memory
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Solution Overview
Problem
In vertically stacked memory array structures, polycrystalline silicon transistors are leaky due to current leakage through grain boundaries, while single crystal silicon cannot be grown on common amorphous dielectric materials used in transistors, and high growth temperatures are incompatible with CMOS components.
Innovation Solution
A silicon wafer is used as a substrate for high-temperature single crystal silicon formation, with a silicon germanium layer grown first, followed by epitaxial growth of single crystal silicon layers in a superlattice structure, allowing precise control and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polycrystalline silicon is used for transistors in vertically stacked memory, then the transistor can be formed on the substrate, but current leakage through grain boundaries occurs resulting in high off-current
Solution Approach 1:
The patent changes the crystalline structure parameter of the silicon material from polycrystalline to single crystal. This fundamental parameter change eliminates grain boundaries entirely, thereby eliminating the leakage pathway through grain boundaries and reducing off-current by three orders of magnitude.
Solution Approach 2:
The patent employs a composite structure consisting of single crystal silicon layers alternating with amorphous dielectric layers (SiO2, Si3N4, or SiON). This composite material approach allows the single crystal silicon to provide low-leakage channels while the dielectric layers provide isolation and structural support.
2Reliability
If single crystal silicon is grown directly on amorphous dielectric materials, then the desired low-leakage structure is achieved, but the growth temperature is too high for CMOS components
Solution Approach 1:
The patent introduces an intermediary silicon germanium (SiGe) layer between the amorphous dielectric substrate and the single crystal silicon layers. This intermediary layer serves as a buffer that enables epitaxial growth at reduced temperatures (below 900°C) compatible with CMOS components, while still allowing the formation of high-quality single crystal silicon with low leakage.
Solution Approach 2:
The patent changes the material composition parameter by introducing germanium into the silicon lattice to form SiGe. This compositional change modifies the growth characteristics, enabling epitaxial growth at lower temperatures that are compatible with existing CMOS processing while still achieving single crystal structure.
3Productivity
If design rules are shrunk to increase memory capacity, then more memory cells fit on the substrate, but available semiconductor space for fabricating memory decreases
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to vertically stacked (3D) memory architecture. By stacking multiple memory layers vertically, the patent increases memory capacity without proportionally increasing the semiconductor footprint, effectively utilizing the third dimension to accommodate additional memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly lower off-current and reduced gate/drain induced leakage, improving transistor performance by three orders of magnitude compared to silicon-based access devices.
Implementation Method 1
a silicon germanium layer grown first, followed by epitaxial growth of single crystal silicon layers
Implementation Method 2
epitaxial growth of single crystal silicon layers in a superlattice structure
Data Source
AI summary
Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.