SiGe Epitaxial Transistor Stress via Recrystallization
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Solution Overview
Problem
Current methods for manufacturing transistors are limited in the level of stress that can be applied to the channel, particularly for N-type and P-type transistors, as the amount of substitutional carbon in SiC is limited, restricting the tensile stress that can be achieved.
Innovation Solution
A transistor manufacturing process involving epitaxial growth of source and drain blocks with a lattice parameter different from the channel material, followed by partial amorphization and recrystallization to impose the lattice parameter of the epitaxial material on the channel, allowing for greater stress application, such as using SiGe to apply tensile stress to a silicon channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If epitaxy of SiC is used to apply tensile stress to silicon channel, then tensile stress is applied to the channel, but the amount of substitutional carbon is limited to about 1% which limits the tensile stress that can be applied
Solution Approach 1:
The invention changes the material composition parameter by using SiGe (silicon-germanium) instead of SiC (silicon-carbide) for the source and drain regions. By adjusting the germanium content in the SiGe alloy, the lattice parameter can be precisely controlled to generate higher tensile stress in the channel while avoiding the 1% substitutional carbon limitation of SiC epitaxy.
Solution Approach 2:
The invention uses composite SiGe material comprising silicon and germanium in varying proportions. This composite approach allows tuning of the lattice parameter between that of pure silicon and pure germanium, enabling optimization of tensile stress application to the channel while maintaining epitaxial compatibility with the silicon substrate.
2Stress or pressure
If different epitaxial materials are used for N-type and P-type transistors, then appropriate stress can be applied to each type, but the manufacturing process becomes more complex
Solution Approach 1:
The invention makes the SiGe epitaxial material universal for both N-type and P-type transistor fabrication. By controlling the germanium concentration in the SiGe layer, the same epitaxial process can generate tensile stress for N-type transistors or compressive stress for P-type transistors, eliminating the need for different epitaxial materials and simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the application of higher stresses than traditional methods, simplifying the transistor manufacturing process and allowing for the production of both N-type and P-type transistors with improved performance by favoring the recrystallization front advancement and reducing the need for protective layers during epitaxy.
Implementation Method 1
a step of forming by epitaxy zones intended to partly form source and drain blocks on the layer comprising the channel
Implementation Method 2
a step of partial amorphization of the sources and drains so as to leave only a crystalline layer at the top of the access
Implementation Method 3
a recrystallization step so that the crystalline layer of the remaining ports mainly imposes its lattice parameter on the layer containing the channel
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A~3
AI summary
A method for fabricating a transistor on a layer of a first crystalline semiconductor material for the fabrication of a channel, deposited on a dielectric layer, the method comprising the steps: - epitaxial growth of regions in a second semiconductor material on the layer of a first crystalline semiconductor material, so as to form source and drain blocks with the layer of a first crystalline semiconductor material on either side of the channel, the second semiconductor material having a lattice parameter different from that of the first semiconductor material, - in-depth amorphization of a portion of the regions in a second semiconductor material so as to retain only a layer of the second crystalline semiconductor material on the surface of the source and drain blocks, and amorphization of the regions of the layer in a first semiconductor material located beneath the regions in the second semiconductor material.- Recrystallization of the source and drain blocks such that the second semiconductor material imposes its lattice parameter on the source and drain zones.