SiGe Tri-Gate Transistor for High Hole Mobility
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Solution Overview
Problem
Current technologies face challenges in producing CMOS integrated circuits with n-channel and p-channel MOSFETs having the same silicon fin body structure and current operating capacity using the same bulk silicon substrate, particularly in enhancing hole mobility for p-channel MOSFETs.
Innovation Solution
A SiGe p-channel tri-gate transistor is developed with a silicon fin on a bulk silicon substrate, featuring a body contact, isolation insulating film, active layer with a specific Si1-xGex composition, gate insulating film, and tri-gate structure to increase hole mobility and enable high-speed, low-power operation, allowing for simultaneous fabrication with n-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon-germanium alloy body is used to enhance carrier mobility, then electron mobility is improved, but hole mobility for p-channel MOSFET is not improved
Solution Approach 1:
The patent applies different material compositions to different regions: the active layer uses Si1-xGex with germanium content x≥0.3 to enhance hole mobility, while the capping layer uses pure silicon or different composition to provide mechanical support and electrical isolation. This local differentiation allows the structure to optimize for p-channel device performance while maintaining overall structural integrity
Solution Approach 2:
The patent changes the germanium concentration parameter x in the Si1-xGex active layer to at least 0.3, which is higher than conventional structures. This parameter change fundamentally alters the band structure and strain characteristics, creating conditions favorable for hole mobility enhancement rather than just electron mobility
2Ease of manufacture
If the same bulk silicon substrate is used for both n-channel and p-channel MOSFETs, then manufacturing simplicity is maintained, but achieving the same current operating capacity for both transistor types is difficult
Solution Approach 1:
The patent creates locally optimized regions within the bulk silicon substrate: p-channel devices receive Si1-xGex active layers with x≥0.3 for hole mobility enhancement, while n-channel devices can receive different compositions or structures. This allows each device type to have optimal characteristics while sharing the same substrate and fabrication process
Solution Approach 2:
The patent develops a universal fabrication process that can produce both n-channel and p-channel MOSFETs on the same bulk silicon substrate. The process uses standard CMOS-compatible steps including selective epitaxial growth, ion implantation, and metallization, making the system versatile for producing complementary transistor pairs with matched performance
3Reliability
If a tri-gate structure is implemented to improve device performance, then control over the channel is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate structure into three distinct gates (front gate and two side gates) that independently control different portions of the channel. This segmentation allows each gate to be formed using separate lithography and deposition steps, making the complex structure manufacturable through modular processing
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional tri-gate configuration where gates wrap around the channel in multiple dimensions. This dimensional change provides superior electrostatic control and channel modulation while maintaining compatibility with standard semiconductor fabrication techniques through careful process sequencing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed, low-power operation with improved hole mobility and body biasing through an integral structure, facilitating the co-fabrication of n-channel and p-channel transistors using the same CMOS process.
Implementation Method 1
the compressive strain of the Si1-xGex active layer is able to enhance the hole mobility
Data Source
AI summary
A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.