SiGe Wafer Stress Compensation via Backside Layer
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Solution Overview
Problem
Current epitaxial deposition techniques for SiGe layers on Si substrates face challenges in reducing cross-hatch and surface roughening, as well as wafer bowing due to thermal expansion mismatch, despite efforts to minimize strain relaxation and dislocation formation.
Innovation Solution
A stress compensating layer is deposited on the backside of the substrate before cooling, with a composition and thickness similar to or matching the heteroepitaxial layer, to counteract stress generated during cooling, thereby controlling wafer bow and improving SiGe layer quality by reducing dislocation density and surface roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a heteroepitaxial layer is deposited on a single crystal substrate, then the crystal structure is improved, but wafer bowing occurs due to thermal expansion mismatch
Solution Approach 1:
A stress compensating layer is deposited on the backside of the substrate to counteract the tensile stress generated by the heteroepitaxial layer during cooling. This layer acts as a counterweight that applies compressive stress to balance the bowing force, thereby maintaining wafer flatness while preserving the crystal structure improvements from epitaxial deposition.
Solution Approach 2:
The stress compensating layer is designed with specific parameters (thickness, composition, deposition temperature) that can be adjusted to control the magnitude and direction of compensating stress. By changing these parameters, the system can optimize the balance between maintaining crystal quality and controlling wafer bowing to within acceptable limits.
2Quantity of substance
If the heteroepitaxial layer thickness is increased, then more material is deposited, but threading dislocation density increases
Solution Approach 1:
The stress compensating layer creates a more uniform stress distribution throughout the wafer structure, which locally stabilizes the crystal lattice and reduces the driving force for dislocation formation. This allows thicker heteroepitaxial layers to be deposited while maintaining lower threading dislocation densities through improved local crystal quality.
3Manufacturing precision
If grading of Ge concentration is applied, then surface roughness is reduced, but cross-hatch intensity increases for higher Ge concentrations
Solution Approach 1:
The stress compensating layer counteracts the stress fields generated by the graded SiGe buffer layer, which reduces the driving force for cross-hatch formation. By balancing the stress distribution, the system can achieve smoother surfaces with reduced cross-hatch intensity even when using higher Ge concentrations in the graded buffer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress compensating layer effectively reduces cross-hatch, surface roughening, and wafer bow, achieving improved crystal quality and uniformity across the SiGe layer, with a final bow within specific limits and significant reduction in threading dislocation density and root mean square roughness.
Implementation Method 1
Because of the difference in thermal expansion coefficient between the heteroepitaxial layer and the substrate, a stress is generated, and the wafer bends to a certain degree resulting in a curvature of the wafer
Implementation Method 2
A crystalline heteroepitaxial layer deposited on a single crystal substrate by epitaxial deposition typically differs from the substrate in several material properties including crystal lattice dimensions
Data Source
AI summary
A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.