SiGe Wafer Stress Compensation and Dislocation Control
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Solution Overview
Problem
The existing methods for depositing SiGe heteroepitaxial layers on silicon substrates fail to adequately address the stress-related issues such as bowing, surface roughening, and dislocation formation during and after the deposition process, particularly affecting the crystal quality and geometry of the wafer, especially for advanced CMOS transistors in sub-45 nm device generations.
Innovation Solution
A method involving the deposition of a stress compensating layer on the backside of the substrate, followed by chemical mechanical polishing and cleaning, and then the deposition of a graded or constant composition SiGe heteroepitaxial layer on the front side, to control stress and improve wafer flatness and nanotopography by adjusting the thickness and Ge concentration of the stress compensating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a heteroepitaxial SiGe layer is deposited on a silicon substrate, then the lattice constant is increased, but threading dislocations and surface roughness are generated due to strain relaxation
Solution Approach 1:
The patent segments the SiGe layer into multiple thinner sub-layers with different Ge concentrations, where each sub-layer is below the critical thickness for strain relaxation. This prevents the formation of threading dislocations while still achieving the desired lattice constant through cumulative effect of multiple layers.
Solution Approach 2:
The patent applies local quality by varying the Ge concentration in different regions of the SiGe layer. The Ge concentration is optimized locally in each sub-layer to control the lattice constant while maintaining strain compatibility with the silicon substrate, thereby preventing dislocation formation in critical areas.
2Object-generated harmful factors
If the Ge concentration in SiGe buffer layer is graded, then the density of threading dislocations is reduced, but the surface roughness and bowing are still affected by stress relaxation
Solution Approach 1:
The patent introduces a stress compensating layer with opposite stress characteristics to counterbalance the stress-induced bowing of the wafer. This layer is specifically designed to provide mechanical compensation for the shape distortion caused by the graded SiGe buffer layer, thereby maintaining wafer flatness.
Solution Approach 2:
The patent employs a composite structure consisting of multiple SiGe sub-layers with different Ge concentrations, combined with a stress compensating layer. This composite material system allows independent optimization of dislocation density (through grading) and wafer shape (through stress compensation).
3Stress or pressure
If annealing steps are applied to fully relax the SiGe buffer, then the stress from lattice mismatch is relieved, but secondary relaxation and surface roughening occur during cooling
Solution Approach 1:
The patent performs preliminary stress management by depositing multiple thin SiGe sub-layers that are each below the critical thickness for strain relaxation. This preliminary structure prevents excessive stress accumulation during deposition, eliminating the need for aggressive annealing that would cause surface roughening during subsequent cooling.
Solution Approach 2:
The patent converts the potentially harmful effect of stress accumulation into a beneficial graded structure. By intentionally creating a gradient of Ge concentrations across multiple sub-layers, the stress is distributed and managed progressively, transforming what would be a harmful stress concentration into a controlled stress distribution that prevents surface roughening.
4Shape
If thin intermediate layers of strained Si are provided to compensate bowing, then the wafer flatness is improved, but the device complexity and process steps increase
Solution Approach 1:
The patent makes the SiGe buffer layer multi-functional by incorporating both the lattice constant control function and the stress compensation function within the same layered structure. The graded Ge concentrations serve dual purposes: controlling lattice parameters and managing stress distribution, thereby eliminating the need for separate bowing compensation layers and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the density of threading dislocations, surface roughness, and bowing, while improving global and local flatness parameters and nanotopography, meeting the stringent specifications for 32 nm device generation wafers.
Implementation Method 1
Because of the difference in thermal expansion coefficient between heteroepitaxial layer and substrate new stress is generated
Implementation Method 2
Secondary relaxation, bowing of the wafer and roughening of the surface are the mechanisms to release this stress
Implementation Method 3
A crystalline heteroepitaxial layer of SiGe deposited on a silicon single crystal substrate by epitaxial deposition
Implementation Method 4
Grading of the Ge concentration in the SiGe layer has been a successful way to reduce the density of TD and Pu and the surface roughness
Data Source
Figure 1
Figure 2~4
AI summary
A method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method comprising steps in the following order: Simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.