Co-integrating Elastic and Plastic Relaxation on SiGe Wafers
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Solution Overview
Problem
Conventional semiconductor device manufacturing faces challenges in defect formation during the plastic relaxation of SiGe layers, particularly in pFET sections with high Ge concentration, which can lead to degraded device performance, and elastic relaxation is not applicable to static random access memory (SRAM) regions where fins are not cut.
Innovation Solution
The method involves co-integration of elastic and plastic relaxation on the same wafer by forming n-doped field effect transistor (nFET) sections with tensile silicon fins on elastically relaxed SiGe substrates in logic regions and plastically relaxed SiGe substrates in SRAM regions, using a combination of etching and epitaxial growth to create fin formations with free surfaces that facilitate relaxation and tension application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If plastic relaxation of SiGe is used in pFET sections with high Ge concentration, then sufficient compressive stress in the channel material is generated, but defect formation occurs during the relaxation process
Solution Approach 1:
The patent applies different relaxation methods to different regions of the same wafer: plastic relaxation is used in logic regions where high Ge concentration is needed for pFET compressive stress, while elastic relaxation is used in SRAM regions to avoid defect formation. This regional differentiation allows each area to have the specific stress characteristics it needs without suffering from the drawbacks of the relaxation method applied elsewhere.
2Reliability
If elastic relaxation of SiGe is used to avoid defect formation, then device performance is maintained, but it is not applicable to SRAM regions where fins are never cut
Solution Approach 1:
The patent implements region-specific relaxation strategies: elastic relaxation is applied to SRAM regions where fins remain intact and performance maintenance is critical, while plastic relaxation is applied to logic regions where fin cutting occurs and compressive stress is the priority. This localized approach allows each device type to receive the appropriate relaxation treatment for its specific requirements.
3Ease of manufacture
If a blanket SiGe layer is grown everywhere on the wafer, then manufacturing simplicity is maintained, but different stress requirements of nFET and pFET sections cannot be met
Solution Approach 1:
The patent maintains a blanket SiGe layer structure for manufacturing simplicity but introduces regional differentiation through selective relaxation methods. By applying elastic relaxation to SRAM regions and plastic relaxation to logic regions, the patent achieves both ease of manufacture (through the blanket layer approach) and differentiated stress control (through region-specific relaxation), resolving the contradiction between manufacturing simplicity and stress requirement fulfillment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates defect generation in logic regions through elastic relaxation while maintaining performance in SRAM regions by applying appropriate stress to silicon channels, enhancing the reliability and efficiency of semiconductor device fabrication.
Implementation Method 1
The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion
Implementation Method 2
Defect formation can be an issue during the plastic relaxation of SiGe
Data Source
AI summary
An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.