Sigma-Delta ADC Chopping Timing to Reduce Noise Aliasing
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Solution Overview
Problem
Conventional chopped sigma-delta analog-to-digital converters (ΣΔ-ADCs) suffer from undesired quantization noise due to aliasing when chopping frequencies are lower than the sampling frequency, leading to noise behavior issues.
Innovation Solution
Adjust the duration of chopping phases in the ΣΔ-ADC to desynchronize the integrator and chopping phases by configuring the timing circuit to adjust the duration of at least one of the first and second chopping phases according to (N/2−k)·Ts or (4n−1)·Ts, where N and n are positive integers, and Ts is the sampling period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional chopping is used in a ΣΔ-ADC to remove offset and low frequency errors, then offset errors and drift are reduced to extremely low levels, but quantization noise aliasing occurs when chopping frequencies are lower than the sampling frequency
Solution Approach 1:
The patent applies periodic chopping action at a frequency lower than the sampling frequency to remove offset errors. The chopping signal periodically switches the analog signal path, enabling offset cancellation while the timing circuit synchronizes this periodic action with the sampling process to manage quantization noise aliasing effects.
Solution Approach 2:
The patent changes the timing parameters of the chopping phases relative to the sampling periods. By adjusting the start times and durations of chopping phases using the timing circuit, the patent modifies when chopping occurs within each sampling period, thereby controlling the aliasing behavior of quantization noise while maintaining offset cancellation benefits.
2Device complexity
If the chopping frequency is reduced below the sampling frequency, then the chopping process can be simplified and offset cancellation is effective, but undesired quantization noise effects occur due to aliasing
Solution Approach 1:
The patent uses periodic chopping at reduced frequency with multiple phases within each sampling period. This periodic structure simplifies the chopping circuit compared to high-frequency alternatives while the multi-phase timing arrangement controls quantization noise aliasing by distributing chopping events across different timing positions within each sampling period.
Solution Approach 2:
The patent segments the chopping period into multiple distinct chopping phases (first chopping phase, second chopping phase, etc.), each with specific timing relationships to the sampling period. This segmentation allows the low-frequency chopping to achieve offset cancellation while the distributed timing of phases manages quantization noise aliasing effects.
3Object-generated harmful factors
If the duration of chopping phases is adjusted to desynchronize with the sampling period, then quantization noise behavior is improved by reducing aliasing, but the timing synchronization becomes more complex
Solution Approach 1:
The timing circuit generates periodic chopping phase signals with durations and start times that are fractional multiples of the sampling period Ts. This periodic timing arrangement desynchronizes chopping from sampling to reduce quantization noise aliasing, while the regular periodic structure keeps the timing circuit implementation manageable through systematic phase relationships.
Data Source
AI summary
A sigma-delta analog-to-digital converter is configured to convert an analog input signal to a digital output signal at a sampling frequency (fs). The sigma-delta analog-to-digital converter includes a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency (fchop=fs/N) to generate a chopped analog signal, where N is a positive integer with N≥1. A chopper period includes a first chopper phase and a second chopper phase. The sigma-delta analog-to-digital converter also includes a timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phases according to (N/2−k)·Ts, with k being an odd integer equal to or larger than 1, and Ts being a sampling period 1/fs of the sigma-delta analog-to-digital converter.