Multiplexed Sigma-Delta ADC Clocking to Prevent Channel Data Mixing
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Solution Overview
Problem
Existing higher-order sigma-delta analog-to-digital converters (ADCs) face challenges in channel multiplexing due to the use of multiple delaying integrators, which leads to incorrect channel multiplexing and data mixing between consecutive full clock cycles.
Innovation Solution
The proposed solution involves determining two channel selection clock sets and delaying local feedback if applied, while applying multiple modulator feedback signals with mutually different timing. This approach prevents data mixing by ensuring that the second channel selection clock set is delayed relative to the first, allowing for correct channel multiplexing in higher-order SDADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delaying integrators are used in higher-order sigma-delta ADCs, then bandwidth and noise performance are improved, but channel multiplexing becomes incorrect and data mixing occurs between consecutive clock cycles
Solution Approach 1:
The patent divides the clocking system into multiple independent clock sets (first clock set with first channel selection clocks, second clock set with second channel selection clocks) that are specifically assigned to different integrators. This segmentation allows each integrator to operate with its own synchronized timing, preventing data mixing while maintaining the benefits of multiple delaying integrators for noise shaping.
Solution Approach 2:
The patent changes the timing parameters of feedback signals by introducing specific delays. The first feedback signal is delayed relative to the second feedback signal, and channel selection clocks are assigned with different phase relationships. This parameter adjustment ensures that feedback from multiple delaying integrators is applied at correct timing intervals, preventing data mixing between channels while preserving bandwidth enhancement.
2Speed
If multiple delaying integrators are used in higher-order sigma-delta ADCs, then bandwidth is increased, but data mixing occurs between consecutive full clock cycles
Solution Approach 1:
The patent implements a sophisticated feedback mechanism where feedback signals from quantizer output are selectively applied to different integrators at different timing intervals. The first feedback signal is applied to the first delaying integrator with a first delay, while the second feedback signal is applied to the second delaying integrator with a second delay. This controlled feedback timing prevents data mixing while maintaining the bandwidth benefits of multiple delaying integrators.
Solution Approach 2:
The patent applies preliminary timing adjustments to feedback signals before they are applied to integrators. By pre-delaying the first feedback signal relative to the second feedback signal, and by assigning specific phase relationships to channel selection clocks, the system ensures that feedback is applied at the correct moment in the sampling cycle, preventing data mixing between consecutive clock cycles while preserving bandwidth.
3Ease of operation
If channel selection clocks are not properly delayed, then multiplexing operation is simplified, but incorrect channel selection and data mixing occur
Solution Approach 1:
The patent introduces dynamic timing control where channel selection clocks are not static but are specifically phased relative to each other. The first channel selection clocks and second channel selection clocks operate with defined phase relationships that dynamically synchronize with the integrator operation cycles. This dynamic timing control maintains ease of multiplexing operation while ensuring accurate channel selection through proper timing alignment.
Data Source
AI summary
A multiplexed sigma-delta analog-to-digital converter (ADC) is provided for digitizing analog input signals of at least two input channels. The ADC includes input circuitry that obtains samples of the input channels and an integrator chain. The integrator chain includes a first delaying integrator and a second delaying integrator. The first delaying integrator processes a sample of one of the two input channels at a time. A first non-delaying integrator is disposed in the integrator chain either between the first delaying integrator and the second delaying integrator or after the second delaying integrator. A clocking arrangement includes a first clock set and a second clock set. Channel selection clocks included in the second clock set are delayed in comparison to the respective channel selection clocks included in the first clock set in order to prevent data from being mixed between consecutive full clock cycles.