Sigma-Delta ADC Data Sharing With Polyphase Filtering for Lower Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed, high-performance continuous time sigma-delta analog-to-digital converters face performance degradation due to feedback digital-to-analog converter (DAC) mismatch and significant power dissipation, especially at high quantizer sampling frequencies, making it challenging to design complex digital and analog interfaces.
Innovation Solution
A continuous time sigma-delta analog-to-digital converter circuit incorporating a single bit quantizer, a single bit digital-to-analog converter (DAC) with a series of flip-flops, a polyphase filter circuit, and a fan out circuit to selectively apply bits to the polyphase filter paths, which reduces power consumption and design complexity by sharing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high quantizer sampling frequency is used to improve conversion speed and performance, then productivity is improved, but power consumption increases exponentially
Solution Approach 1:
The patent segments the high-speed conversion task into multiple parallel polyphase filter paths, each operating at a lower effective rate. The modulator output is distributed across N parallel paths that process signals simultaneously, allowing the system to achieve high overall throughput while each individual path consumes less power, thus resolving the exponential power increase at high sampling frequencies.
Solution Approach 2:
The patent employs periodic sampling and processing across the polyphase paths, where each path processes a specific phase of the sampled signal. By distributing the processing load periodically across multiple paths rather than concentrating all processing in a single high-speed path, the system reduces peak power consumption while maintaining high conversion speed.
2Manufacturing precision
If single bit quantization and single bit DAC are used to improve linearity and reduce mismatch, then manufacturing precision is improved, but device complexity increases due to higher sampling frequency requirements
Solution Approach 1:
The patent divides the single bit DAC output into multiple parallel polyphase paths, where each path processes a portion of the signal. This segmentation allows the simple single bit DAC to achieve high effective resolution through the combined output of multiple paths, maintaining linearity while distributing the complexity across parallel simpler stages rather than requiring a single complex high-speed stage.
Solution Approach 2:
The patent merges the outputs of multiple polyphase filter paths to reconstruct the final high-resolution digital signal. By combining the results from N parallel paths, each processing a fraction of the total signal, the system achieves the equivalent performance of a high-resolution single-path system while using simpler single bit quantization and DAC elements in each path.
3Measurement precision
If high sampling frequency is used to improve dynamic range and bandwidth, then measurement precision is improved, but power dissipation in analog and digital circuits increases significantly
Solution Approach 1:
The patent segments the high-frequency sampling task across multiple polyphase paths, where each path operates at a lower effective sampling rate. This division allows the system to achieve high dynamic range and bandwidth equivalent to a single high-speed path while each individual path dissipates less power, reducing total power loss in both analog and digital circuit sections.
Solution Approach 2:
The polyphase filter structure provides multi-functionality by simultaneously performing filtering, decimation, and signal distribution across parallel paths. This universal structure handles multiple signal processing functions in an integrated manner, improving dynamic range through coherent processing while minimizing redundant circuitry that would increase power dissipation.
Data Source
AI summary
A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.