Sigma-Delta ADC Decimation for Asynchronous Output Rates
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Solution Overview
Problem
Existing oversampling sigma delta analog to digital converters face challenges in providing variable asynchronous output data rates while maintaining high signal to noise ratios and linearity, as they often require inflexible sampling and output data rates that do not align with application-specific requirements.
Innovation Solution
A converter circuit comprising an oversampling sigma delta modulator, a transposed polynomial decimator, and an integer decimator, which allows for variable asynchronous output data rates by using a transposed polynomial filter and digital phase locked loop to track the ratio between the desired output data rate and the oversampled rate, thereby attenuating noise and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional oversampling sigma delta converters use fixed sampling and output data rates, then circuit complexity is reduced, but adaptability to different application requirements deteriorates
Solution Approach 1:
The patent implements dynamic sample rate conversion by using a digital phase locked loop to continuously track the ratio between the desired output data rate and the oversampled rate, allowing the converter to adapt to variable asynchronous output requirements while maintaining circuit efficiency through dynamic adjustment rather than multiple fixed-rate circuits
Solution Approach 2:
The patent changes the operational parameters of the converter by using a transposed polynomial filter with dynamically adjustable coefficients that are determined based on the tracked ratio, enabling the same circuit to operate at multiple output data rates by simply changing the filter parameters rather than reconfiguring the entire circuit
2Productivity
If decimation is performed to reduce output data rate, then productivity is improved, but measurement precision of the signal to noise ratio deteriorates
Solution Approach 1:
The patent applies preliminary filtering using the transposed polynomial filter before final decimation to pre-attenuate out-of-band noise and prevent aliasing, ensuring that the decimation process maintains high signal to noise ratio by preparing the signal in advance rather than relying solely on post-decimation filtering
Data Source
AI summary
A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.