Sigma-Delta ADC Mute-Period DEM Control for Lower Power

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Solution Overview

Problem

Existing Sigma-Delta (Σ-Δ) Analog-to-Digital Converters (ADCs) face issues with power consumption due to the continuous operation of Dynamic Element Matching (DEM) circuits during mute periods, leading to poor Spur-Free Dynamic Range (SFDR) performance and unnecessary power usage.

Innovation Solution

Incorporating a control circuit that disables the DEM circuit during mute periods and employing multiple DEM algorithms with a switching circuit to dynamically select the feedback signal, reducing power consumption and enhancing SFDR performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DEM circuit continuously runs the DWA algorithm during mute periods, then the nonlinear problem is resolved and capacitance mismatch is reduced, but power consumption increases unnecessarily

Engineering Contradiction:
Improvenonlinear problem resolutionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by enabling the DEM circuit to operate intermittently rather than continuously. The control circuit detects mute periods and disables the DEM circuit during these intervals, while keeping it active during normal signal periods. This periodic operation maintains the nonlinear problem resolution capability when needed while eliminating unnecessary power consumption during mute periods.

Inventive Principle:
Principle #19Periodic action

2Reliability

If the DEM circuit runs continuously, then feedback signal is maintained, but SFDR performance deteriorates due to in-band tone generation

Engineering Contradiction:
Improvefeedback signal continuityVSAvoidin-band tone
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent uses periodic action to suspend the DWA algorithm during mute periods, which eliminates the continuous operation that generates in-band tones. By stopping the algorithm only when the input signal is muted, the system maintains feedback signal readiness while avoiding the harmful in-band tone generation that occurs with continuous operation.

Inventive Principle:
Principle #19Periodic action

3Object-affected harmful factors

If multiple DEM algorithms are implemented, then SFDR performance is improved, but device complexity increases

Engineering Contradiction:
ImproveSFDR performanceVSAvoidcircuit structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies dynamics by implementing multiple DEM algorithms (such as DWA and alternative algorithms) and dynamically selecting which algorithm to execute based on the operating condition. The control circuit determines whether the input signal is in a mute period and selects the appropriate algorithm accordingly. This dynamic approach improves SFDR performance by having algorithm options available while avoiding the complexity of permanently implementing all algorithms simultaneously.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses local quality by applying different DEM algorithms to different operational contexts. Instead of using a single algorithm for all conditions, the system applies specific algorithms locally based on the input signal state. During mute periods, one algorithm may be selected, while during active signal periods, another algorithm is used, optimizing performance for each local condition without requiring all algorithms to operate simultaneously.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10693490B1Sigma-delta analog-to-digital converter and operation method thereof
Publication Date: 2020.06.23 FARADAY TECH CORP
  • US10693490B1 patent drawing
  • US10693490B1 patent drawing
  • US10693490B1 patent drawing

AI summary

A Sigma-Delta (Σ-Δ) analog-to-digital converter (ADC) and operation method thereof are provided. The Σ-Δ ADC includes a Σ-Δ modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the Σ-Δ modulator is configured to receive an analog signal. The Σ-Δ modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the Σ-Δ modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the Σ-Δ modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.