Sigma-Delta ADC Dither Circuit for Limit Cycle Suppression
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Solution Overview
Problem
Sigma-delta modulators in analog-to-digital converters (ADCs) introduce limit cycles that cause undesired distortions and errors, and existing dithering methods increase power consumption and load capacitance due to additional transistors and circuits.
Innovation Solution
A sigma-delta modulator based ADC with an integrated analog dither circuit that uses a digital dither generator to provide multi-level dither signals, reducing limit cycles by controlling current division through resistors and transistors, minimizing power consumption and load capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital dither signals are added through multiple input transistors in series, then limit cycles are reduced, but load capacitance increases and power consumption increases
Solution Approach 1:
The patent combines the dither signal injection function with the existing input transistor structure by integrating the digital dither generator output directly into the quantizer input stage. This merging approach allows dither signals to be injected without adding separate series transistors, thereby reducing the total load capacitance on the integrator while still achieving limit cycle reduction through the dither noise mechanism.
2Reliability
If multiple input transistors are used to receive digital dither signals, then dithering effect is achieved, but fixed load capacitance increases
Solution Approach 1:
The patent makes the existing input transistors serve dual functions: they simultaneously handle the main signal path and the digital dither signals. By configuring the input transistors to receive both the integrator output and dither signals, the design achieves dithering functionality without requiring additional dedicated transistors, thus avoiding increased load capacitance while maintaining effective limit cycle suppression.
3Reliability
If extra current source apparatus is added to the quantizer input stage, then dither noise can be injected, but extra power and peripheral circuits are required
Solution Approach 1:
The patent employs the existing current sources already present in the quantizer input stage to provide the dither noise injection function. By configuring these existing current sources to respond to digital dither signals, the design achieves dithering without requiring additional current source apparatus, thereby eliminating the need for extra power consumption and peripheral circuits while maintaining effective dither noise injection.
Data Source
AI summary
The disclosed invention is a sigma-delta modulator based ADC and a dithering method thereof. An analog dither circuit of an input stage in a quantizer, which is configured to perform dithering, receives an integrator output signal from an output of an integrator and a plurality of digital dither signals from digital dither generator, and employs these signals to produce multi-level analog dither signals via the operation of a plurality of transistors as switches coupled with a plurality of resistors coupled in series. The multi-level analog dither signals can prevent, reduce, or eliminate limit cycle in the sigma-delta modulator based ADC. Furthermore, disclosed invention does not require fixed load capacitance, resulting in no extra power consumption and solve the problem as the kickback noise variation.