Continuous-Time Sigma-Delta ADC Feedback DAC for Jitter and Noise
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Solution Overview
Problem
Conventional continuous-time delta-sigma analog-to-digital converters (ADCs) face challenges in reducing current consumption and sensitivity to clock jitter and thermal noise, particularly in their feedback DAC implementations.
Innovation Solution
The design incorporates two switched-capacitor DACs with a mutual delay in time, operating as a single combined DAC within the continuous-time ΔΣ ADC, with one DAC in an inner loop to reduce sensitivity to excess loop delay and the other in an outer loop to minimize thermal noise and clock jitter sensitivity, thereby optimizing noise performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional switched-current or switched-capacitor feedback DACs are used in continuous-time delta-sigma ADCs, then the quantized analog feedback signal can be generated, but the current consumption increases and sensitivity to clock jitter and thermal noise worsens
Solution Approach 1:
The feedback DAC is segmented into two separate switched-capacitor DACs (first SC-DAC and second SC-DAC) that operate with mutual time delay. Each SC-DAC handles a portion of the feedback signal generation, allowing the system to reduce peak current consumption while distributing thermal noise across different time intervals. This segmentation enables lower power operation while maintaining signal integrity through the combined effect of both DACs.
Solution Approach 2:
The two switched-capacitor DACs are operated with periodic time delay between their switching actions. The first SC-DAC switches during one time interval while the second SC-DAC switches during a subsequent time interval, creating a periodic pattern. This periodic operation allows the system to spread current consumption over time, reducing instantaneous power peaks, while the time-delayed switching patterns help decorrelate and reduce the impact of thermal noise and clock jitter on the overall feedback signal.
2Productivity
If higher sampling rates are achieved in continuous-time delta-sigma ADCs, then the bandwidth and resolution improve, but the power consumption and sensitivity to noise increase
Solution Approach 1:
The feedback signal generation is segmented into two time-staggered operations using the first and second SC-DACs. By dividing the high-rate feedback task into two sequential operations with time delay, each DAC operates at reduced current levels compared to a single high-speed DAC, thereby achieving high effective sampling rates while reducing individual component power consumption and overall thermal noise.
Solution Approach 2:
The switched-capacitor DACs employ periodic switching with controlled time delays to achieve high sampling rates. The periodic switching pattern allows the capacitors to be charged and discharged in a rhythmic fashion, enabling high-frequency operation. The time-delayed periodic actions of the two DACs combine to produce the high-rate feedback signal while distributing the power consumption and noise characteristics across multiple switching events.
3Reliability
If conventional single switched-capacitor DAC is used, then the circuit complexity is low, but the robustness to delays and noise performance deteriorates
Solution Approach 1:
The feedback DAC functionality is segmented into two separate switched-capacitor DACs with distinct switching timings. This segmentation provides robustness to delays because the time-delayed operation of the two DACs creates a more stable average feedback signal that is less sensitive to individual switching variations. The dual-SC-DAC structure also distributes thermal noise across different time intervals, improving noise performance while maintaining a relatively simple switched-capacitor implementation for each unit.
Solution Approach 2:
The system employs feedback through the continuous-time loop filter that processes the combined output from both SC-DACs. The loop filter integrates the time-delayed feedback signals from the first and second SC-DACs, automatically compensating for timing variations and delays. This feedback mechanism enhances robustness to delays and noise without requiring complex additional circuitry, as the existing loop filter structure naturally handles the combined feedback signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced power consumption and improved robustness to delays and noise, enabling increased sampling rates or dynamic range at a lower cost, while maintaining robust closed-loop performance.
Implementation Method 1
Each of the two switched capacitor DACs is arranged to be charged with a charge proportional to the sample of the digital output signal. A first of the switched capacitor DACs is arranged to be switched in to the continuous-time analog network for transfer of its charge to the continuous-time analog network
Data Source
Figure 1~3
Figure 4~5
Figure 6~7
AI summary
A continuous-time ΣΔ-ADC (1) is disclosed. It comprises a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ΔΣ-ADC (1) at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (5). Furthermore, the ΔΣ-ADC (1) comprises one or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5). Moreover, the ΔΣ-ADC (1) comprises a continuous-time analog network (20) arranged to generate the analog input signal to the quantizer (5) based on the feedback signal(s) from the one or more DACs (10a-b) and an analog input signal to the ΔΣ-ADC (1). At least one DAC (10b) of the one or more DACs (10b) comprises two switched-capacitor DACs (40, 50) arranged to operate on the same input but with a mutual delay in time. A corresponding radio receiver circuit (100), a corresponding integrated circuit (200), and a corresponding radio communication apparatus (300, 400) are also disclosed.