Sigma-Delta ADC Gain-Scaled Feedback for Fewer Quantizer Levels
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Solution Overview
Problem
Multi-level sigma-delta Analog-to-Digital Converter (ADC) circuits face limitations in increasing the number of quantization levels due to the complexity of the quantizer, which introduces substantial delay and instability, making it challenging to achieve high accuracy while maintaining low complexity.
Innovation Solution
A multi-level sigma-delta ADC design with a direct path and feedback paths that include amplification blocks with specific gain factors, allowing for a reduced number of quantization levels in the quantizer, such as 8 levels, while maintaining the accuracy and complexity of the converter, by using a flash converter with comparators equal to the number of quantization levels minus one, and employing Digital-to-Analog converters to facilitate feedback signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of quantization levels is increased to reduce quantization noise, then measurement precision is improved, but device complexity increases due to the need for more comparators and higher quantizer accuracy
Solution Approach 1:
The quantizer is divided into multiple stages with different gains. The first quantizer stage processes signals with gain G1 and the second quantizer stage processes with gain G2, where G1 ≠ G2. This segmentation allows each stage to handle a portion of the dynamic range, reducing the complexity of each individual quantizer while maintaining overall high precision conversion.
Solution Approach 2:
The patent changes the gain parameter of the quantizer stages. By using different gain values (G1 and G2) in different stages, the system can achieve high measurement precision without requiring a single complex high-resolution quantizer. The gain modulation allows the same hardware to effectively handle multiple quantization levels.
2Measurement precision
If the quantizer accuracy is increased to achieve higher conversion accuracy, then measurement precision is improved, but the delay introduced by the quantizer increases causing instability
Solution Approach 1:
The conversion process is segmented into multiple stages with different quantizers operating at different gains. This allows the system to achieve high accuracy through multiple lower-complexity stages rather than a single high-accuracy stage, reducing the overall delay and improving stability.
3Measurement precision
If flash converter with many comparators is used to achieve high quantization levels, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
Instead of using a single flash converter with many comparators, the patent segments the conversion into multiple stages with fewer comparators each. The first quantizer uses gain G1 with a set of comparators, and the second quantizer uses gain G2 with another set of comparators. This segmentation dramatically reduces the total number of comparators needed while achieving the same or better precision.
Solution Approach 2:
The patent changes the gain parameter between stages to optimize the distribution of quantization levels. By using different gain values, the system can achieve high effective resolution without requiring a proportional increase in the number of comparators in each stage.
Data Source
AI summary
A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.