Sigma-Delta ADC Common Reference for Rail-to-Rail Linearity
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Solution Overview
Problem
Existing continuous-time, incremental sigma-delta ADCs lack rail-to-rail linearity, limiting their ability to accurately digitize wide-ranging analogue inputs without requiring costly linearity-correction processing.
Innovation Solution
A continuous-time sigma-delta ADC design featuring a resistor-capacitor integrator with a differential amplifier and a clocked comparator, where both amplifier and comparator reference inputs are maintained at a common voltage derived from the converter reference input, utilizing a voltage divider and resistor ratios to achieve near rail-to-rail linearity and small chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single capacitor is used in the integrator to minimize chip area, then the chip area is reduced, but the linearity range is limited and cannot achieve rail-to-rail linearity
Solution Approach 1:
The patent changes the reference voltage parameter by introducing a common reference voltage node that is shared between the differential amplifier and comparator. This parameter change enables the system to achieve rail-to-rail linearity without requiring multiple capacitors, thus resolving the contradiction between small chip area and wide linearity range.
2Manufacturing precision
If separate reference voltages are used for the amplifier and comparator, then each component can be optimized independently, but the circuit complexity increases and chip area expands
Solution Approach 1:
The patent merges the reference voltage sources for the differential amplifier and comparator into a single common reference voltage node. This combining approach reduces circuit complexity and chip area while maintaining the ability to achieve high linearity through the shared reference potential.
3Manufacturing precision
If rail-to-rail linearity is achieved through multiple capacitors, then the linearity range is improved, but the chip area and power consumption increase
Solution Approach 1:
The patent achieves rail-to-rail linearity by changing the reference voltage parameter configuration rather than increasing the number of capacitors. This approach maintains low power consumption characteristic of single-capacitor designs while expanding the linearity range to cover the full rail-to-rail input range.
Data Source
AI summary
An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.