Sigma-Delta ADC Time-Constant Tuning for PVT-Stable Transfer Functions
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Solution Overview
Problem
Existing analog-to-digital converters, particularly Nyquist-rate ADCs, face limitations in effective number of bits due to matching issues and process, voltage, and temperature variations, while oversampling ADCs like sigma-delta ADCs are more popular for applications requiring large dynamic range, but they require large die space and are sensitive to pulse width variations.
Innovation Solution
A sigma-delta ADC with a variable input resistor and a switched-capacitor bias current generator that uses a successive-approximation-register logic circuit to tune the resistance of a variable tuning resistor, reducing sensitivity to pulse width variations and maintaining constant noise and signal transfer functions, while minimizing die space and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sigma-delta ADC uses a fixed input resistor and fixed bias current, then the circuit is simple, but the noise and signal transfer functions vary with process, voltage, and temperature
Solution Approach 1:
The patent applies dynamics by making the input resistor value可调 (adjustable) through a resistor array controlled by a tuning circuit. The resistor can be dynamically adjusted to compensate for PVT variations, ensuring that the noise and signal transfer functions remain constant despite environmental changes. This transforms a static circuit into a dynamic one that adapts to maintain performance.
Solution Approach 2:
The patent implements feedback through a tuning circuit that receives feedback about the actual performance of the ADC and adjusts the resistor value accordingly. The tuning circuit monitors the system and makes real-time adjustments to maintain constant transfer functions, creating a closed-loop control system that ensures reliability.
2Reliability
If an oversampling ADC is used to achieve large dynamic range, then the dynamic range is improved, but the die space and power consumption increase
Solution Approach 1:
The patent applies parameter changes by adjusting the resistor value to optimize the balance between dynamic range and resource consumption. By tuning the resistor parameter, the system can achieve the desired dynamic range performance without requiring excessive die space or power, as the same hardware can be optimized for different operating conditions.
3Ease of operation
If pulse width variations occur in the clock signal, then the ADC can operate with simple clocking, but the transfer functions become sensitive to these variations
Solution Approach 1:
The tuning circuit provides feedback that compensates for pulse width variations. By monitoring the actual transfer function performance and adjusting the resistor value in response, the system becomes insensitive to clock signal variations, maintaining reliable operation even with simple clocking schemes.
Solution Approach 2:
The patent uses parameter changes by adjusting the resistor value to compensate for the effects of pulse width variations. This dynamic parameter adjustment allows the system to maintain constant transfer functions regardless of clock signal variations, decoupling performance from clock timing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution maintains consistent performance across process, voltage, and temperature variations, improving noise and signal transfer functions, and reduces die space and power consumption, making it suitable for applications like microphones.
Implementation Method 1
a switched-capacitor bias current generator configured to be clocked by a pair of complementary clock signals to generate a bias current that is proportional to a capacitance of the integration capacitor divided by a pulse width of the complementary clock signals
Implementation Method 2
a variable tuning resistor configured to conduct a mirrored version of the bias current to develop a tuning voltage across the variable tuning resistor
Data Source
AI summary
A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.