Sigma-Delta Resampling Clock Synchronization for Digital Signals
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Solution Overview
Problem
Existing synchronization methods for electronic systems with diverse clock frequencies, such as those used in portable devices, face challenges including increased power consumption, circuit complexity, and signal degradation due to noise, especially when using high-frequency master clocks or resampling techniques.
Innovation Solution
A synchronizing digital device utilizing a multi-bit sigma-delta modulator and an All Digital Phase Locked Loop (ADPLL) to synchronize slave devices with a system bus clock frequency, employing a resampler controlled by a sigma-delta modulator to align resampling frequency with the bus clock, effectively filtering noise and reducing complexity without additional analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-frequency master clock signal is sent to all slave devices, then synchronization robustness is improved, but power consumption increases and device autonomy is reduced
Solution Approach 1:
The patent replaces the traditional mechanical/electrical approach of distributing high-frequency clock signals through dedicated lines with a digital signal processing approach. Slave devices generate their own clock signals locally and use digital filtering to extract the master clock frequency, eliminating the need for high-power dedicated clock distribution lines and reducing overall system power consumption while maintaining synchronization robustness
Solution Approach 2:
The patent introduces a digital filter as an intermediary component in slave devices that processes the received data signal to extract the master clock frequency. This intermediary allows slave devices to achieve synchronization without directly receiving high-frequency clock signals, thereby reducing power consumption while maintaining synchronization accuracy
2Reliability
If resampling is carried out within slave devices using slow signals, then circuit complexity increases, but synchronization is achieved
Solution Approach 1:
The patent extracts only the essential synchronization function from complex resampling circuits. Instead of implementing full resampling chains with frequency multiplication and interpolation, the invention extracts the master clock frequency directly from the data signal using simple digital filtering, removing unnecessary circuit complexity while preserving synchronization capability
Solution Approach 2:
The patent changes the approach from time-domain resampling to frequency-domain filtering. By transforming the synchronization problem into a frequency extraction problem, the system achieves synchronization with simpler circuits that filter rather than resample, significantly reducing device complexity
3Measurement precision
If resampling and conversion operations are performed, then frequency synchronization is attempted, but noise is introduced that degrades the signal
Solution Approach 1:
The patent converts the potentially harmful effect of multiple conversion stages into a benefit by using a single digital filtering operation. The filter naturally suppresses out-of-band noise and spurious signals while extracting the desired clock frequency, turning what could be a noise-generating complex conversion chain into a noise-reducing simple filter
Solution Approach 2:
The patent replaces analog resampling and conversion operations that introduce noise with digital filtering operations. The digital filter processes the signal in the digital domain, avoiding the noise-generating analog conversion stages while achieving the same frequency synchronization precision
Data Source
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Figure 3
AI summary
A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (FCKB); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (FCKJ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (FRS); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (FRS) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .