Common-Mode Translation in Sigma-Delta ADC Input Circuits
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Solution Overview
Problem
Continuous-time sigma-delta analog-to-digital converters face reliability issues due to mismatched common mode levels between input signals and the converter's operational range, leading to signal degradation and potential failure during start-up, overload, or power supply loss, especially when interfacing with RF chips.
Innovation Solution
A system and method for common mode translation in continuous-time sigma-delta ADCs, incorporating a loop filter with an input RC network, a Gm-C/Quantizer/DAC circuit, a common mode level adjust circuit, and a tuning circuit that adjusts the common mode level to match the desired level by generating a compensation voltage based on the difference between the input signal's common mode level and the desired level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the common mode level of the input signal is adjusted to match the converter's operational range, then reliability is improved, but device complexity increases due to the need for additional common mode level adjust circuitry
Solution Approach 1:
The patent introduces a common mode level adjust circuit that acts as an intermediary between the input signal and the continuous-time sigma-delta ADC. This circuit translates the common mode level of the input signal to match the converter's operational range, thereby improving reliability without requiring fundamental changes to the ADC architecture. The adjust circuit includes translation circuitry that selectively adjusts the common mode level based on control signals.
Solution Approach 2:
The common mode level adjust circuit is designed to be dynamically controllable, allowing the common mode level to be adjusted based on the specific input signal characteristics and operating conditions. The circuit responds to control signals that indicate whether adjustment is needed, enabling adaptive operation rather than fixed configuration.
2Ease of manufacture
If a low-voltage process is used for fabrication, then manufacturing cost is reduced, but reliability deteriorates due to high common mode levels exceeding supply voltage
Solution Approach 1:
The common mode level adjust circuit performs preliminary action by translating the common mode level of the input signal before it reaches the continuous-time sigma-delta ADC. This prevents high common mode levels from causing reliability issues in low-voltage fabricated circuits, allowing the use of cost-effective low-voltage fabrication processes without sacrificing reliability.
3Measurement precision
If the loop filter maintains the summing junction at the common mode level during normal operation, then signal processing accuracy is improved, but vulnerability increases during start-up, overload, or power supply loss when the loop cannot maintain the common mode level
Solution Approach 1:
The common mode level adjust circuit provides beforehand cushioning by preparing the input signal with the appropriate common mode level before it enters the loop filter. This protective measure ensures that even when the feedback loop cannot maintain the summing junction at the common mode level during transient conditions, the input signal remains within safe operating ranges, preventing reliability issues.
Data Source
AI summary
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.