Sigma-Delta DAC Phase Alignment to Reduce Sign-Bit Pulses
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Solution Overview
Problem
Sigma-Delta Digital-to-Analog Converters (DACs) experience unwanted secondary effects, such as sign-bit pulses, when the frequency margin between the digital-clock frequency and the cut-off frequency decreases, which can lead to reduced performance and increased signal bandwidth, and existing solutions like higher order low-pass filters or increased digital-clock frequencies are economically unfavorable.
Innovation Solution
Adjusting the phase relationship between the data waveform and the signum function by aligning transitions approximately halfway between rising and falling edges, or setting them out of phase by approximately 90° plus or minus an integer multiple of 180°, before multiplying them to produce a digital input for the SD DAC, effectively reducing the amplitude of sign-bit pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the frequency margin between digital-clock frequency and cut-off frequency is decreased to increase signal bandwidth, then signal bandwidth is improved, but sign-bit pulses are generated causing reduced performance
Solution Approach 1:
The patent changes the phase parameter of the digital input signal by introducing a phase shift between the data waveform and signum function. This parameter change allows the system to operate with reduced frequency margin while avoiding sign-bit pulses, thus resolving the contradiction between signal bandwidth and performance.
Solution Approach 2:
The patent applies preliminary phase adjustment to the digital input signal before it enters the sigma-delta DAC. By pre-aligning or pre-misaligning the phase relationship between waveforms, the system prevents sign-bit pulse generation in advance, allowing broader signal bandwidth without performance degradation.
2Reliability
If higher order low-pass filters are used to reduce sign-bit pulses, then performance is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the sign-bit pulse generation mechanism from the filter domain and addresses it at the digital input stage. By removing the phase relationship that causes sign-bit pulses before the signal enters the DAC, the system eliminates the need for higher order filters, reducing device complexity while maintaining performance.
Solution Approach 2:
Instead of using complex filters to eliminate sign-bit pulses after they are generated, the patent inverts the approach by preventing their generation at the source through phase adjustment of the digital input signal. This simplifies the overall system architecture.
3Reliability
If digital-clock frequency is increased to reduce sign-bit pulses, then performance is improved, but power consumption and cost increase
Solution Approach 1:
The patent changes the phase parameter of the digital input signal to prevent sign-bit pulse generation. This allows the system to maintain performance at lower digital-clock frequencies, thereby reducing power consumption without sacrificing reliability.
Data Source
AI summary
For a sigma-delta digital-to-analog converter (SD DAC) that includes a voltage output and a low-pass filter having a given order, methods and systems for reducing a sign-bit pulse at the voltage output of the SD DAC without requiring use of a higher order low-pass filter are disclosed. A method includes receiving a first waveform and a second waveform, the first and second waveforms having a first phase relationship; setting the first phase relationship between the first and second waveforms to a second phase relationship by aligning at least one of the first and second waveforms such that a transition of the second waveform is approximately half way between a rising edge and adjacent falling edge of the first waveform; upon setting the second phase relationship, multiplying the first and second waveforms to produce a digital input; and providing the digital input to the SD DAC.