Sigma-Delta Modulator Feedback Compensation for Clock Jitter
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Solution Overview
Problem
Conventional continuous-time sigma-delta modulators face challenges with limited input impedance, low linearity, and high power consumption, particularly in sensor applications where high input impedance and robustness against clock jitter are required.
Innovation Solution
A sigma-delta modulator design incorporating an instrumentation amplifier-based integrator with a 1-bit quantizer and FIR digital-to-analog converters for feedback compensation, which reduces clock jitter and high-frequency quantization noise, and allows for low power operation with a small integration capacitor, enhancing linearity and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional active RC integrators are used, then the circuit has better linearity and larger output swing, but the input impedance is limited
Solution Approach 1:
The patent combines the advantages of both active RC and Gm-C integrators by merging their core functionalities. The instrumentation amplifier provides high input impedance characteristic of Gm-C integrators, while the active RC feedback path maintains good linearity. This merging resolves the contradiction by achieving both high input impedance and acceptable linearity in the same integrator structure.
2Measurement precision
If Gm-C-based integrators are used, then the input impedance is infinite and the circuit is faster, but the linearity is low due to open loop of Gm cell
Solution Approach 1:
The patent introduces feedback mechanisms to improve the linearity of Gm-C-based integrators. By feeding back a portion of the output signal to the input through carefully designed feedback paths, the open-loop nonlinearity of the Gm cell is compensated, thereby improving overall linearity while maintaining the high input impedance advantage.
3Speed
If high-speed amplification stages are used in discrete-time sigma-delta converters, then the conversion speed is improved, but the energy consumption increases
Solution Approach 1:
The patent employs periodic switching and clocked operation in the discrete-time sigma-delta converter. By using periodic action with optimized clocking schemes and switched-capacitor circuits, the converter achieves high conversion speed through oversampling and noise shaping, while energy consumption is reduced by confining amplification to brief periodic intervals rather than continuous high-speed operation.
4Measurement precision
If multi-bit digital-to-analog converter is used, then the feedback signal resolution is improved, but the linearity deteriorates due to element mismatch
Solution Approach 1:
The patent segments the multi-bit digital-to-analog converter into multiple parallel paths, each handling a portion of the feedback signal. This segmentation allows the use of simpler, more mismatch-resistant circuit elements in each path while collectively achieving high resolution. The segmented structure reduces the impact of individual element mismatches on overall linearity.
Data Source
AI summary
A sigma-delta modulator. The signal-delta modulator includes: an integrator having an instrumentation amplifier designed to receive an input signal to be modulated at a first input and to receive a feedback signal at a second input, wherein the integrator is designed to generate an integrator signal using the input signal and the feedback signal; a quantizer, which is designed to generate a quantizer signal in accordance with the integrator signal; a first FIR digital-to-analog converter, which is designed to generate the feedback signal in accordance with the quantizer signal; a first compensation device, which is designed to compensate for an excess loop delay in accordance with the quantizer signal; and a second compensation device, which comprises a second FIR digital-to-analog converter, which is designed to compensate for a clock cycle shift of the feedback signal in accordance with the quantizer signal.