Digital Sigma-Delta Modulator Feedback for Stable Single-Bit Operation
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Solution Overview
Problem
Current digital sigma-delta modulators face challenges in achieving high-order stability with single-bit quantization, particularly in the GHz frequency range, due to quantizer overload and non-linear effects, which limits their resolution and signal-to-noise ratio in mobile communication systems.
Innovation Solution
A digital sigma-delta modulator design incorporating a systolic array with error and signal feedback loops, utilizing FIR filters with specific transfer functions and coefficients realized through wired bit-shifts, enables stable operation with single-bit quantization by attenuating out-of-band noise and ensuring poles remain within the unit circle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher-order sigma-delta modulators are used to achieve high signal-to-noise ratio and bandwidth, then resolution and signal-to-noise ratio improve, but stability deteriorates due to quantizer overload and non-linear effects
Solution Approach 1:
The modulator is divided into multiple parallel first-order sub-modulators instead of using a single higher-order modulator. Each sub-modulator operates independently with its own quantizer, preventing quantizer overload while collectively achieving the desired high signal-to-noise ratio and bandwidth performance through parallel operation.
2Ease of manufacture
If single-bit quantization is used to reduce device complexity and cost, then manufacturing precision improves, but stability deteriorates in higher-order modulators
Solution Approach 1:
The system uses multiple parallel first-order modulators with single-bit quantizers instead of a single higher-order modulator. This segmentation allows each simple single-bit quantizer to operate within its stable range while the parallel structure collectively achieves high resolution, preventing quantizer overload and maintaining stability.
Solution Approach 2:
Multiple first-order modulator outputs are combined through addition to achieve the equivalent performance of a higher-order modulator. This merging of parallel simple structures creates the desired high signal-to-noise ratio and bandwidth while maintaining the stability benefits of single-bit quantization in each individual modulator.
Data Source
AI summary
A digital sigma-delta modulator (100) for modulating a digital input signal (x) is described. The digital sigma-delta modulator (100) comprises a quantizer (115) for quantizing an input signal (s) and producing a quantized output signal (y) at a first output (110) and an error output signal (−q) at a second output (165), at least one feedback loop (120, 125) connected to an input adder (140) and the first outputs (110) and the second output (165) of the quantizer (115) and a feedback filter (130, 135) in the at least one feedback loop (120, 125). The input adder (140) produces the sum signal (s) by adding the digital input signal (x) at an input (105) and output signals of the at least one feedback loop filters (130,135).