Sigma-Delta Modulator Inner Loop for Excess Loop Delay Compensation
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Solution Overview
Problem
Conventional sigma delta modulators (SDMs) face instability due to unaccounted parasitic poles and excess loop delay, which complicates noise transfer function compensation and leads to unstable behavior, especially when the end of the DAC pulse exceeds one sampling period.
Innovation Solution
The introduction of a feedback 'inner loop' with a track-and-hold (T/H) circuit controlled by the inverse clock signal, coupled between the comparator and DAC, provides additional compensation for excess loop delay by allowing feedback even when the DAC pulse exceeds one sampling period, using a T/H cell with input switches and a current steering circuit to manage differential signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SDM architecture is used with standard clocking, then the circuit is simple, but excess loop delay causes instability when DAC pulse exceeds one sampling period
Solution Approach 1:
The patent segments the single clocking function into two separate clock signals: a first clock signal for the latch and a second (inverse) clock signal for the T/H circuit. This segmentation allows independent control of sampling and latching operations, enabling stability compensation for excess loop delay while maintaining manageable circuit complexity through modular clock distribution.
Solution Approach 2:
The patent introduces a track-and-hold (T/H) circuit as an intermediary component between the comparator and DAC. This T/H circuit, controlled by the inverse clock signal, acts as a mediator that compensates for excess loop delay by holding the comparator output during the DAC pulse period, thereby stabilizing the feedback loop without requiring fundamental architectural changes.
2Duration of action of moving object
If the DAC pulse exceeds one sampling period, then more time is available for signal processing, but unaccounted parasitic poles and excess delay lead to unstable behavior
Solution Approach 1:
The patent applies preliminary action by using the inverse clock signal to pre-charge and prepare the T/H circuit before the actual sampling period begins. The T/H circuit tracks the comparator output during the first clock phase and holds it during the second clock phase, proactively compensating for the extended DAC pulse duration and associated excess delay before instability can occur.
Solution Approach 2:
The patent implements a feedback mechanism where the T/H circuit continuously monitors the comparator output and adjusts its hold function based on the inverse clock signal. This feedback loop compensates for parasitic poles and excess delay by dynamically adjusting the held signal to match the intended feedback value, maintaining stability even when DAC pulse exceeds one sampling period.
Data Source
AI summary
A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.