Hybrid Sigma-Delta Interface RC Network for Noise Isolation

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Solution Overview

Problem

Conventional hybrid sigma-delta converters face performance degradation due to the interface between continuous-time and discrete-time stages, leading to reduced Signal to Noise and Distortion Ratio (SNDR) performance, primarily caused by differential and common mode stress from the discrete-time filter's intrinsic sample-and-hold stage, which also results in high current consumption and incompatibility with low voltage operations.

Innovation Solution

An interface circuit using a passive resistor-capacitor (RC) network acts as a bi-directional low-pass filter to absorb noise stress and reduce peak currents, effectively isolating the continuous-time stage from discrete-time stage interference by attenuating high-frequency 'kickback' signals and differential mode stress, while maintaining compatibility with low voltage operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a discrete-time filter with intrinsic sample-and-hold stage is used in hybrid sigma-delta converter, then filtering performance is improved, but differential and common mode stress on continuous-time stage increases causing SNDR degradation

Engineering Contradiction:

Improvefiltering performanceVSAvoiddifferential and common mode stress

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

A buffer stage is introduced as an intermediary between the continuous-time filter and discrete-time filter. This buffer isolates the continuous-time stage from the differential and common mode stress generated by the discrete-time sample-and-hold circuit, preventing SNDR degradation while maintaining the filtering performance of the discrete-time stage.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The interface between continuous-time and discrete-time stages is segmented by introducing a separate buffer stage. This segmentation allows the continuous-time and discrete-time circuits to operate independently without mutual interference, resolving the stress issue while preserving filtering functionality.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If discrete-time filter stage is incorporated into hybrid sigma-delta ADC, then noise shaping capability is improved, but noise coupling from discrete-time to continuous-time stage increases

Engineering Contradiction:

Improvenoise shaping capabilityVSAvoidnoise coupling

Core Design Contradiction:

Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The buffer stage acts as a mediator that prevents noise generated by the discrete-time filter from coupling back to the continuous-time stage. This isolation maintains the noise shaping benefits of the discrete-time filter while eliminating harmful noise feedback.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If conventional hybrid sigma-delta converter architecture is used, then high resolution and low distortion are achieved, but current consumption increases and low voltage operation compatibility decreases

Engineering Contradiction:

Improveresolution and distortion performanceVSAvoidcurrent consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The buffer stage enables efficient current management by isolating the continuous-time and discrete-time stages. This allows for optimized current distribution where each stage operates at its optimal current level, reducing total current consumption while maintaining high resolution and low distortion performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution significantly reduces voltage and current spikes reflected from the discrete-time stage to the continuous-time stage, enhancing SNDR performance and current efficiency, thereby improving the overall operation of hybrid sigma-delta converters.

Implementation Method 1

An interface circuit using a passive resistor-capacitor (RC) network acts as a bi-directional low-pass filter to absorb noise stress and reduce peak currents

Methodology Applied

Scientific EffectLow-pass filtering: Filter (electronic)

Implementation Method 2

The interface circuit further reduces the coupling of noise generated from the operation of the discrete-time circuit to the preceding continuous-time circuit

Methodology Applied

Scientific EffectResistive damping: Damping

Data Source

PatentUS7609189B1Interface for hybrid sigma-delta data converter

Publication Date: 2009.10.27 MARVELL ASIA PTE LTD

AI summary

A hybrid sigma-delta converter that includes a continuous-time circuit that processes an input signal and generates a first output signal, an interface circuit that receives the first output signal from the continuous-time circuit and filters the first output signal thereby generating a second output signal, and a discrete-time circuit that processes the second output signal received from the interface circuit. The interface circuit further reduces the coupling of noise generated from the operation of the discrete time circuit to the preceding continuous-time circuit.