Sigma-Delta Modulator Latch Architecture for Excess Loop Delay
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Solution Overview
Problem
High-speed continuous-time sigma-delta ADCs face instability and reduced resolution due to excess loop delay, which is exacerbated by the need for high-gain, power-hungry amplifiers in conventional ELD compensation methods, leading to undesirable delays and power consumption.
Innovation Solution
A current-mode multi-path excess loop delay compensation technique that eliminates the need for pre-amplifiers by using local time-interleaved latches and current-domain feedback loops, allowing for complementary output from paired latches and reducing delay, while simplifying clocking schemes and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ELD compensation methods using high-gain amplifiers are employed, then loop delay compensation is achieved, but power consumption increases and additional delay is introduced
Solution Approach 1:
The patent extracts and removes the pre-amplifier stage from the conventional ELD compensation architecture. By eliminating this high-power component, the invention achieves loop delay compensation without the associated high power consumption and additional delay, directly resolving the technical contradiction between stability and power usage.
Solution Approach 2:
The invention changes the operational parameters by using time-interleaved latches with optimized timing sequences instead of continuous high-gain amplification. This parameter change allows the system to achieve the same compensation function with lower power consumption and reduced delay, addressing both stability and energy efficiency requirements.
2Reliability
If pre-amplifiers are used in ELD compensation, then loop delay is compensated, but regeneration time is reduced and metastability errors increase
Solution Approach 1:
The patent applies preliminary action by pre-charging and pre-discharging the latches in a time-interleaved manner before the actual quantization operation. This preliminary preparation ensures that the latches are ready to operate immediately, maximizing regeneration time and reducing metastability errors without requiring high-gain pre-amplifiers.
Solution Approach 2:
The invention implements periodic action through time-interleaved clocking sequences that alternately charge and discharge different latch pairs. This periodic operation ensures sufficient regeneration time for each latch while maintaining continuous operation, thereby improving resolution without the time loss associated with conventional pre-amplifier-based compensation.
3Productivity
If conventional clocking schemes are used, then quantization operation is performed, but clock jitter affects performance and power consumption increases
Solution Approach 1:
The patent segments the quantization operation into multiple time-interleaved phases, each handled by dedicated latch pairs with independent clocking. This segmentation allows each phase to operate with relaxed timing requirements, reducing the impact of clock jitter on overall performance while maintaining high quantization speed and accuracy.
Data Source
AI summary
A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.