Sigma-Delta Modulator Limit Cycle Detection With Periodic Dithering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Sigma delta modulators suffer from limit cycles, which current methods fail to detect and remove effectively without introducing unwanted noise or reducing signal-to-noise ratio, especially in high-order noise shaping techniques.
Innovation Solution
A circuit and method for detecting limit cycles by comparing output signal values over iterations and applying a disturbance to the input to remove them, using memory means and detection mechanisms that allow for accurate and efficient limit cycle detection and removal without constant dithering, applicable to both feedforward and feedback designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current methods (such as constant dithering) are used to prevent limit cycles, then limit cycle occurrence is reduced, but unwanted noise is introduced and signal-to-noise ratio deteriorates
Solution Approach 1:
The patent applies periodic dithering only when limit cycles are detected, rather than continuous dithering. The dither signal is applied periodically at intervals determined by the detection mechanism, which checks for limit cycle conditions at regular intervals. This periodic application eliminates limit cycles when present while avoiding continuous noise addition.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the sigma-delta modulator is monitored to detect limit cycle conditions. Based on this feedback detection, the dithering mechanism is activated or deactivated dynamically. The detection circuit monitors the output signal and provides feedback control to the dithering element, ensuring dithering is applied only when necessary.
2Reliability
If constant dithering is applied to remove limit cycles, then limit cycles are prevented, but dynamic range is reduced
Solution Approach 1:
The dithering is applied periodically rather than continuously, with activation triggered only when limit cycle detection occurs. This intermittent application preserves the full dynamic range during normal operation while still providing limit cycle removal capability when needed.
Solution Approach 2:
The patent changes the dithering parameter (amplitude and presence) based on the detected state of the modulator. When no limit cycle is detected, dithering is absent or minimal; when detected, dithering amplitude increases to break the limit cycle. This dynamic parameter adjustment maintains dynamic range while enabling limit cycle removal.
3Manufacturing precision
If high-order noise shaping techniques are used, then quantization noise is shaped into high frequencies, but limit cycles become more difficult to detect and remove
Solution Approach 1:
The patent introduces a detection circuit as an intermediary between the high-order modulator output and the final output. This intermediary monitors specific characteristics of the output signal to detect limit cycles, bridging the gap between the complex high-order modulation and the simpler limit cycle detection requirement.
Solution Approach 2:
The detection mechanism monitors specific parameters of the output signal (such as bit pattern repetition, amplitude variations, or spectral characteristics) to identify limit cycles in high-order modulators. By changing the monitoring parameters to suit high-order characteristics, the system can detect limit cycles despite the complexity introduced by high-order noise shaping.
Data Source
AI summary
A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behavior has been observed, and major changes to design are not normally required to implement the detection mechanism.