Multiphase Clock Division Using Sigma-Delta Phase Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional frequency synthesizers face performance limitations due to clock jitter, which degrades signal quality and can lead to system failures, especially when clock signals are propagated across multiple components.
Innovation Solution
The implementation of a frequency synthesizer circuit with a multiphase divider and sigma-delta modulator that phase-shifts clock signals by a predetermined fractional amount, reducing quantization noise and increasing the bandwidth of the phase-locked loop to mitigate oscillator noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional multiplication factor is used between output clock and input clock in a frequency synthesizer, then non-integer multiples of reference frequency can be generated, but clock jitter increases and timing precision deteriorates
Solution Approach 1:
The patent segments the fractional division process into multiple integer division stages. Instead of performing a single fractional division that causes jitter, the circuit performs multiple integer divisions in sequence, where each stage divides by an integer factor. This segmentation eliminates the quantization noise and timing precision degradation associated with direct fractional division, while still achieving the overall fractional frequency multiplication effect.
2Area of stationary object
If clock signals are propagated across multiple components in a system, then frequency distribution is achieved, but jitter propagates and system reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by performing multiple integer division operations in advance before the clock signal is distributed to multiple components. By completing the precise fractional frequency synthesis through staged integer divisions before distribution, the circuit ensures that the clock signal has minimal jitter from the outset. This preliminary precision processing prevents jitter propagation across the system, maintaining signal quality even as the clock is distributed widely.
3Device complexity
If a single delta-sigma fractional-N PLL is used for local oscillator generation, then circuit complexity is reduced compared to cascaded integer-N PLLs, but inherent performance limitations due to fractional multiplication remain
Solution Approach 1:
The patent substitutes the traditional mechanical/mathematical fractional multiplication operation with a digital sequence of integer division operations. Instead of using a fractional-N PLL that inherently suffers from quantization noise and timing errors, the circuit uses multiple integer-N division stages controlled by digital logic. This substitution maintains the simplified single-PLL structure while eliminating the performance limitations of fractional multiplication, achieving both low complexity and high precision.
Data Source
AI summary
An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.