Sigma-Delta PWM Modulator With Dithering for Low-Amplitude Signals

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Solution Overview

Problem

Sigma-delta circuits with PWM modulation face inefficiencies due to constraints on minimum pulse duration, leading to reduced output power efficiency and inability to transfer low-amplitude signals effectively.

Innovation Solution

Incorporating a second sigma-delta stage upstream of the PWM quantizer to control the minimum dynamics, compensating quantization errors, and using a dither signal generator to enhance noise performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the minimum pulse duration constraint is enforced in PWM applications, then the power stage efficiency deteriorates due to excessive switching, but the signal transfer capability for low-amplitude signals is improved

Engineering Contradiction:
Improvepower stage efficiencyVSAvoidsignal transfer capability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The dither signal is added preliminarily to the input signal before PWM quantization, preparing the signal in advance to ensure that even low-amplitude signals exceed the minimum pulse width threshold. This preliminary modification prevents the need for excessive switching while maintaining signal transfer capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of the input signal by adding a dither component, transforming the original signal into a modified signal with enhanced dynamics. This parameter change ensures that the signal maintains sufficient amplitude to generate valid PWM pulses without causing excessive switching in the power stage.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If dithering is applied to improve noise performance, then the signal transfer for low-amplitude signals is improved, but the device complexity increases

Engineering Contradiction:
Improvenoise performanceVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dither signal generation function is merged with the existing sigma-delta modulator architecture. The dither signal is generated using the same quantization resources already present in the system, combining multiple functions into a unified structure rather than adding separate dedicated hardware.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system uses its own internal quantization noise and existing circuit components to generate the dither signal, making the system self-sufficient. The quantizer that would otherwise be a source of noise is repurposed to generate a beneficial dither signal, eliminating the need for external dithering hardware.

Inventive Principle:
Principle #25Self-service

3Reliability

If the pulse duration is prolonged to meet minimum transferable pulse requirements, then the signal transfer capability is improved, but the power stage efficiency deteriorates

Engineering Contradiction:
Improvesignal transfer capabilityVSAvoidpower stage efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

By adding the dither signal preliminarily, the system ensures that pulses meet the minimum duration requirement before they reach the PWM quantizer, eliminating the need for post-processing prolongation operations that would cause excessive switching and energy loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7830289B2Sigma-delta modulator for PWM applications with minimum dynamical control and dithering
Publication Date: 2010.11.09 STMICROELECTRONICS SRL
  • US7830289B2 patent drawing
  • US7830289B2 patent drawing
  • US7830289B2 patent drawing

AI summary

The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.