Sigma-Delta PWM Generator for High Resolution With Lower Power
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Solution Overview
Problem
Existing PWM signal generators face challenges in achieving high-resolution signals with low power dissipation, as high-frequency clocks required for high resolution result in significant power consumption, and methods like multi-phase delay locked loops complicate circuitry and require calibration for process, voltage, and temperature variations.
Innovation Solution
The use of sigma-delta circuits to refine both the period and duty cycle of PWM signals, combined with a threshold mapper and pulse generator, allows for high-resolution PWM generation with lower frequency clocks, reducing circuit complexity and power consumption by producing a direct-drive modulation with fewer harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency PWM clock is used to achieve high-resolution PWM signals, then the PWM resolution is improved, but the power dissipation increases significantly
Solution Approach 1:
The patent divides the PWM generation process into multiple phases using a multi-phase delay locked loop. The single PWM clock cycle is segmented into multiple smaller periods, allowing high-resolution PWM signals to be generated without requiring a proportionally high clock frequency, thus reducing power dissipation while maintaining resolution
Solution Approach 2:
The patent introduces an additional dimension of time by using multiple phases within each clock cycle. Instead of relying solely on increasing clock frequency to achieve resolution, the system distributes PWM signal generation across multiple phases (e.g., four phases), effectively multiplying the resolution capability without proportionally increasing power consumption
2Loss of energy
If a multi-phase delay locked loop is used to achieve high-resolution PWM with lower frequency clock, then the power dissipation is reduced, but the circuit complexity increases due to additional logic and calibration requirements
Solution Approach 1:
The delay locked loop is designed to automatically adjust and calibrate itself without external intervention. The system self-calibrates the analog delay chain to compensate for process, voltage, and temperature variations, eliminating the need for manual calibration procedures and reducing the complexity of external calibration circuitry
Solution Approach 2:
The patent implements feedback mechanisms within the delay locked loop that continuously monitor and adjust the phase delays to maintain accuracy. This feedback system automatically compensates for environmental variations and manufacturing tolerances, reducing the need for complex external calibration circuits and manual adjustment mechanisms
Data Source
AI summary
Techniques are provided herein for generating PWM signals. Furthermore, a direct-drive method is disclosed in which a PWM signal is generated as a differential signal made up of OUTP and OUTN signals, where OUTP is a copy of OUTN but shifted in time by half a period. The PWM signal is generated by passing each of an input period and an input duty cycle through corresponding sigma-delta circuits to generate a refined period and a refined duty cycle, respectively. In some example cases, a threshold mapper uses a lookup table (LUT) or similar mechanism to select timing thresholds for rise times and fall times for each of the OUTP and OUTN signals, where the timing thresholds are selected based on the refined period and the refined duty cycle. In some example cases, a pulse generator generates the OUTP and OUTN signals based on the timing thresholds.