Randomized Sampling in Sigma-Delta Converters for Aliasing Rejection
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Solution Overview
Problem
Sigma-delta modulators face interference due to aliasing when dealing with non-bandlimited input signals, as conventional methods like active antialiasing filters and jittered sampling clocks are insufficient in eliminating interference close to the sampling frequency.
Innovation Solution
Implementing a sigma-delta converter with a sampling controller that actsuates the sampling circuit to sample the input signal at partially random times, effectively increasing the sampling frequency and reducing aliasing effects without the need for an antialiasing filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an active antialiasing filter is used to limit the input bandwidth, then aliasing is reduced, but device complexity increases
Solution Approach 1:
The patent extracts the antialiasing function from a separate filter circuit and integrates it into the sampling circuit itself. The sampling circuit directly limits the input bandwidth through its sampling mechanism, eliminating the need for a dedicated active antialiasing filter while maintaining aliasing reduction effectiveness.
Solution Approach 2:
The sampling circuit is given multiple functions: it performs the primary sampling operation and simultaneously acts as an antialiasing filter by limiting the input bandwidth. This multi-functionality reduces the overall device complexity by eliminating separate filter components.
2Object-affected harmful factors
If a sampling clock with jitter is used to reduce aliasing, then some interference is reduced, but reliability decreases because interference close to the sampling frequency cannot be reliably eliminated
Solution Approach 1:
The patent changes the sampling frequency parameter dynamically by using a dithered sampling clock that varies the sampling frequency within a range. This parameter change approach reliably eliminates interference close to the sampling frequency by ensuring that no fixed frequency component consistently aliases into the signal band, unlike fixed jitter which has limited effectiveness.
3Ease of operation
If discrete-time sampling at a certain sampling frequency is used, then the sampling process is simple, but aliasing occurs when the input signal is not bandlimited
Solution Approach 1:
The patent applies preliminary action by incorporating bandwidth limiting directly into the sampling process. The sampling circuit is configured to inherently limit the input bandwidth before sampling occurs, preventing aliasing from the outset while maintaining the simplicity of the sampling operation. This is achieved through the sampling switch and capacitor configuration that naturally filters high-frequency components.
Data Source
AI summary
Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.