CT Sigma-Delta ADC Self-Calibration for RC Spread Compensation
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Solution Overview
Problem
Continuous-time sigma-delta analog-to-digital converters (CT ΣΔ ADCs) in CMOS technology are sensitive to process variations and temperature changes, leading to instability and reduced signal-to-noise ratio due to variations in RC time constants, requiring calibration but existing calibration methods are slow and time-consuming.
Innovation Solution
A CT ΣΔ ADC with digital self-calibration means, using variable capacitance and resistance elements that adjust based on digital word values to maintain optimal RC product, estimating in-band noise and iteratively adjusting capacitance or resistance to stabilize the converter without external calibration equipment or dedicated test signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If RC integrators are used in deep-submicron CMOS technology, then the converter can operate at lower power consumption, but the RC time constant varies significantly due to process variations and temperature spread
Solution Approach 1:
The patent uses variable capacitance elements (such as switched capacitor banks) and variable resistance elements (such as switched resistor banks) that allow the RC time constant to be dynamically adjusted. During calibration, the capacitance or resistance values are modified to compensate for process variations and temperature effects, thereby maintaining a stable RC time constant while operating in low-power deep-submicron CMOS technology
2Measurement precision
If the RC time constant is increased to reduce quantization noise, then the signal-to-noise ratio improves, but the loop filter becomes unstable
Solution Approach 1:
The patent implements dynamic adjustment of the RC time constant through variable capacitance and resistance elements controlled by calibration circuits. The system can adaptively tune the RC value during calibration to achieve the optimal balance between noise reduction and stability, and then maintain this optimized setting during normal operation, preventing the loop filter from becoming unstable
3Stability of the object's composition
If the RC time constant is decreased to improve loop stability, then the loop filter becomes stable, but quantization noise shifts to the bandwidth reducing signal-to-noise ratio
Solution Approach 1:
The patent employs variable capacitance elements (such as switched capacitor banks) and variable resistance elements that enable precise adjustment of the RC time constant. The calibration circuit determines the optimal RC value that maintains loop stability while keeping quantization noise outside the signal bandwidth, thereby preventing SNR degradation
4Reliability
If analog calibration methods are used to compensate for RC variations, then the RC time constant can be adjusted, but the calibration process is slow and time-consuming
Solution Approach 1:
The patent replaces slow analog calibration methods with a digital calibration approach. A calibration circuit injects test signals and measures the actual RC time constant, then uses digital control signals to adjust the variable capacitance or resistance elements accordingly. This digital-based calibration process is significantly faster and more precise than traditional analog methods
Data Source
AI summary
A continuous-time sigma-delta analog-to-digital converter (CV) including i) a signal path (SP) having at least one combiner (C1) for combining analog signals to convert with feedback analog signals, at least two integrators (H1, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) having at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (C1). Each integrator (H1, H5) having variable capacitance means arranged to be set in chosen states defined by the values of a digital word, to present the chosen capacitances.