Sigma-Delta Reference Clocking for Fractional Synthesis in Integer-N PLLs
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Solution Overview
Problem
Existing systems for fractional frequency synthesis, such as those using sigma-delta modulation, require dedicated fractional-N PLLs, which increase design complexity, power consumption, and cost, and have limited frequency resolution due to the frequency of the VCO, making them inefficient for applications like high-speed optical transceivers.
Innovation Solution
A circuit that uses a programmable frequency divider and Sigma-Delta modulator to generate a modulated reference clock, which is then processed by an integer-N Phase Lock Loop (PLL) to achieve fractional-N frequency synthesis without the need for a dedicated fractional-N PLL, allowing for reduced design effort, power consumption, and cost by leveraging existing PLLs and digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated fractional-N PLL is used for fractional frequency synthesis, then frequency resolution is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the fractional-N synthesis functionality into the existing integer-N PLL by adding a sigma-delta modulator that controls the programmable frequency divider. This combines the reference clock generation and frequency division functions into a single integrated structure, eliminating the need for a separate dedicated fractional-N PLL while achieving fractional frequency resolution.
Solution Approach 2:
The existing integer-N PLL is made universal by enabling it to perform both integer and fractional frequency synthesis through the addition of the sigma-delta modulator. The programmable frequency divider can operate in different modes (integer division and fractional division with noise shaping), allowing the same hardware to serve multiple frequency synthesis needs.
2Measurement precision
If a dedicated fractional-N PLL is used for fractional frequency synthesis, then frequency resolution is improved, but power consumption increases
Solution Approach 1:
The patent merges the fractional-N synthesis functionality into the existing integer-N PLL by adding a sigma-delta modulator that controls the programmable frequency divider. This combines the reference clock generation and frequency division functions into a single integrated structure, eliminating the need for a separate dedicated fractional-N PLL while achieving fractional frequency resolution.
Solution Approach 2:
The existing PLL infrastructure serves dual purposes - it provides both the phase locking function and the frequency synthesis function. The sigma-delta modulator utilizes the existing PLL components (VCO, frequency divider, phase detector) to achieve fractional frequency control without requiring additional power-hungry dedicated fractional synthesis hardware.
3Adaptability or versatility
If a dedicated fractional-N PLL is used, then fractional frequency synthesis is achieved, but hardware footprint increases
Solution Approach 1:
The patent merges the fractional-N synthesis functionality into the existing integer-N PLL by adding a sigma-delta modulator that controls the programmable frequency divider. This combines the reference clock generation and frequency division functions into a single integrated structure, eliminating the need for a separate dedicated fractional-N PLL while achieving fractional frequency resolution.
Solution Approach 2:
The existing integer-N PLL is made universal by enabling it to perform both integer and fractional frequency synthesis through the addition of the sigma-delta modulator. The programmable frequency divider can operate in different modes (integer division and fractional division with noise shaping), allowing the same hardware to serve multiple frequency synthesis needs.
4Adaptability or versatility
If sigma-delta modulation is applied to VCO frequency in traditional fractional-N PLL, then fractional frequency synthesis is achieved, but frequency resolution is limited by VCO frequency
Solution Approach 1:
Instead of applying sigma-delta modulation to the VCO frequency as in traditional fractional-N PLL, this patent inverts the approach by applying sigma-delta modulation to the reference clock frequency before it enters the integer-N PLL. This inversion allows the frequency resolution to be determined by the reference clock frequency and the programmable divider ratio rather than being limited by the VCO frequency, achieving finer frequency resolution.
Data Source
AI summary
A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.