CT Sigma-Delta Modulator Self-Calibration via Incremental ADC Reconfiguration
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Solution Overview
Problem
Continuous-time sigma-delta modulators face challenges in reducing sensitivity variation due to process variations, requiring tuning of circuit elements, and existing calibration methods often need external reference signals and additional circuitry.
Innovation Solution
A sigma-delta modulator arrangement that converts a continuous-time sigma-delta modulator into a first-order incremental sigma-delta analog-to-digital converter, allowing for tuning of modulator stage coefficients without an external reference signal, using a digital integrator and switches to reconfigure the modulator, and incorporating tuning elements like resistor trim arrays for easy adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a continuous-time sigma-delta modulator is used to achieve lower power consumption and higher signal bandwidth, then power efficiency and bandwidth are improved, but sensitivity variation due to process variations increases requiring tuning
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the coefficients of the modulator stages through digital control. The system varies parameters such as the feedback coefficients (k1, k2) and integrator gains to compensate for process variations, thereby maintaining stable sensitivity while preserving the low power consumption advantage of continuous-time modulators
Solution Approach 2:
The patent implements feedback mechanisms where the output of the modulator is fed back through digital processing to adjust the input coefficients. This feedback loop enables automatic calibration of the modulator parameters to counteract sensitivity variations caused by process variations, ensuring reliable operation without increasing power consumption
2Reliability
If tuning of circuit elements is performed to reduce sensitivity variation, then sensitivity stability is improved, but device complexity and additional circuitry increase
Solution Approach 1:
The patent replaces traditional analog tuning circuits with digital control mechanisms. Instead of using complex analog variable components and external reference signals, the system uses digital coefficient adjustment through simple switches and digital-to-analog converters, significantly reducing circuit complexity while maintaining sensitivity stability
Solution Approach 2:
The patent enables self-calibration of the modulator parameters using internally generated signals rather than external reference sources. The system uses its own output signal processed through a digital filter to generate calibration references, eliminating the need for additional external circuitry and reducing overall device complexity
3Measurement precision
If existing calibration methods using external reference signals are used, then calibration accuracy is improved, but chip area and current consumption increase
Solution Approach 1:
The patent makes the modulator stages multi-functional by enabling them to operate in both normal signal processing mode and calibration mode. The same hardware blocks perform dual functions: processing input signals during normal operation and generating calibration references during tuning, thereby eliminating the need for separate dedicated calibration circuitry and reducing chip area
Solution Approach 2:
The patent merges the calibration function with the signal processing function by using the modulator's own internal signals for both purposes. The output signal serves dual roles as both the processed output and as a reference for calibration, combining multiple functions into a single integrated system that reduces overall chip area and current consumption
Data Source
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AI summary
The sigma-delta modulator arrangement (100)comprises a continuous-time sigma-delta modulator (CT_SDM)with at least one modulator stage, a digital integrator(Int_d)and a given number of switches(Sw1,…,Sw8). The switches (Sw1,…,Sw8) are arranged and configured to convert the continuous-time sigma- delta modulator (CT_SDM)into a first order incremental sigma- delta analog-to-digital converter (INC_ADC) comprising the digital integrator(Int_d). At least a first modulator stage (M_1)of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator (CT_SDM), comprises at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.