Sigma-Delta Converter Feedback Using a Single-Bit DAC
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Solution Overview
Problem
Conventional sigma-delta converters consume significant power and occupy large chip area due to the use of multi-bit DACs, which leads to mismatch errors and increased signal-to-noise ratio and total harmonic distortion, necessitating complex dynamic element matching techniques that increase design costs and power consumption.
Innovation Solution
A sigma-delta converter design incorporating a single-bit digital-to-analog converter (DAC) in the feedback path and a feed-forward coefficient circuit that varies the feed-forward coefficient based on the gain control signal, eliminating the need for dynamic element matching techniques and reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit DACs are used in sigma-delta converters, then conversion precision is improved, but power consumption increases and chip area increases
Solution Approach 1:
The multi-bit DAC is segmented into multiple single-bit DACs, each handling a different bit position. This segmentation allows parallel processing of multiple bits using simple single-bit DAC structures, reducing the complexity and power consumption of each individual DAC while maintaining the overall multi-bit conversion capability through time-interleaved operation
Solution Approach 2:
The patent implements dynamic element matching (DEM) techniques that dynamically rearrange and allocate DAC elements based on their actual performance characteristics. This dynamic adaptation compensates for mismatches and non-ideal behaviors, maintaining high conversion precision while allowing the use of simpler, lower-power single-bit DAC structures instead of complex multi-bit DACs
2Measurement precision
If multi-bit DACs are used in sigma-delta converters, then conversion precision is improved, but chip area increases
Solution Approach 1:
The multi-bit DAC function is segmented across multiple single-bit DAC units operating in parallel or time-interleaved fashion. Each single-bit DAC requires minimal circuitry (essentially a switch and capacitor), dramatically reducing the area per bit compared to a traditional multi-bit DAC. The combined area of multiple single-bit DACs is much smaller than a single multi-bit DAC achieving the same resolution
Solution Approach 2:
Instead of implementing a complex multi-bit DAC structure, the patent uses multiple copies of simple single-bit DAC units. Each copy handles a specific bit position, and the overall multi-bit output is synthesized by combining these simple copies. This copying approach leverages the area efficiency of single-bit structures while achieving multi-bit precision through parallel composition
3Reliability
If dynamic element matching techniques are implemented, then mismatch errors are reduced, but device complexity increases and power consumption increases
Solution Approach 1:
The DEM system performs self-characterization and self-correction by automatically measuring the actual weights and offsets of each DAC element and using this information to dynamically allocate elements to code positions. This self-service capability eliminates the need for external calibration equipment or complex manual adjustment mechanisms, reducing overall system complexity while maintaining high reliability through automatic mismatch compensation
Data Source
AI summary
A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.