Switched-Capacitor Sigma-Delta Converter With Single-DAC Feedback
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Solution Overview
Problem
Existing sigma-delta converters for seismic signal detection face challenges in low-power consumption, high sensitivity to noise, and increased power consumption due to complex architectures and additional load on the quantizer comparator, particularly in second-order architectures with multiple branches and active amplifiers.
Innovation Solution
A second-order switched-capacitor sigma-delta converter architecture with a reduced number of branches, a single digital-to-analog converter (DAC), and minimal operational amplifiers, where the second switched capacitor stage amplifies and adds the input signal upstream of the quantization stage, eliminating additional load and noise sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple branches and active amplifiers are used in second-order sigma-delta converter architecture, then signal processing capability is improved, but power consumption increases
Solution Approach 1:
The patent combines the adder and amplifier functions into a single switched-capacitor stage. The second switched-capacitor stage performs both signal addition and amplification in one integrated circuit block, eliminating the need for separate active amplifiers and reducing overall power consumption while maintaining signal processing capability.
Solution Approach 2:
The patent extracts and eliminates unnecessary active amplifiers from the traditional second-order sigma-delta converter architecture. By using switched-capacitor circuits alone for both addition and amplification functions, the design removes power-hungry active components while preserving the essential signal processing functions.
2Adaptability or versatility
If additional load is added at quantizer input, then signal processing flexibility is improved, but noise sensitivity increases
Solution Approach 1:
The patent converts the potential harm of additional load into a benefit by using the switched-capacitor adder to provide both signal processing flexibility and impedance transformation. The adder structure, while adding functionality, actually reduces noise sensitivity by maintaining low impedance at the quantizer input through proper capacitor sizing and switching timing.
3Measurement precision
If complex architecture with multiple DACs is used, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a single DAC that serves multiple functions in the feedback path. The same DAC is used for both feedback signals to the first and second integrators, eliminating the need for multiple DACs while maintaining conversion accuracy through proper feedback signal distribution and timing control.
Data Source
AI summary
A sigma-delta converter may include an input node, a switched capacitor input stage integrating a difference signal between an input signal from the input node and a feedback signal representing an output signal, and a switched capacitor adder coupled downstream from the switched capacitor input stage and generating a sum signal based upon the input signal with a signal generated by the switched capacitor input stage. The sigma-delta converter may include a switched capacitor output stage amplifying the sum signal and generating an analog amplified signal, a quantization stage coupled in cascade to the switched capacitor output stage and generating the output signal as a digital replica of the analog amplified signal, and a circuit generating the feedback signal as an analog replica of the output signal.