Sigma-Delta ADC Split-Bit Conversion Without Error Correction
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Solution Overview
Problem
Existing sigma-delta analog to digital conversion technologies are complex and require error correction logic, especially when dealing with DC signals, which increases hardware complexity and reduces efficiency.
Innovation Solution
The proposed solution involves a dual-ADC system where a first ADC with a constant reference voltage provides high-order bits and a second ADC with a variable reference voltage provides low-order bits, eliminating the need for error correction logic by separately sampling and converting upper and lower bits using a sigma-delta ADC and a single-slope ADC, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single ADC with error correction logic is used for high precision conversion, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the ADC system into two separate functional units: a first ADC for high-order bit conversion and a second ADC for low-order bit conversion. This segmentation eliminates the need for complex error correction logic while achieving high precision through coordinated operation of the two simpler units.
Solution Approach 2:
The patent introduces a digital signal processor as an intermediary that receives digital signals from both ADCs, performs addition operations, and generates the final high-resolution digital signal. This intermediary handles the complexity of combining precision data from both converters.
2Reliability
If error correction logic is added to handle DC signals, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the conversion task into two parallel ADC paths, each handling specific bit ranges. This segmentation allows DC signals to be processed reliably without requiring additional error correction logic, as each ADC operates within its optimized range.
Solution Approach 2:
The dual-ADC configuration provides universal functionality for handling both AC and DC signals with high reliability. The system can process various signal types without requiring specialized error correction circuits, as the parallel ADC architecture inherently handles different signal characteristics.
3Device complexity
If a dual-ADC system is used to simplify conversion, then device complexity is reduced, but measurement precision may worsen
Solution Approach 1:
The patent segments the digital output into high-order bits from the first ADC and low-order bits from the second ADC. By properly weighting and summing these segmented components in the digital signal processor, the system achieves high measurement precision equivalent to or exceeding a single high-resolution ADC.
Solution Approach 2:
The patent transitions from a single-dimension conversion approach to a two-dimensional approach by using two ADCs operating in parallel with different reference voltages. The digital signal processor combines these two-dimensional inputs to produce a high-resolution output, effectively adding a dimension to the conversion process that enhances precision.
Data Source
AI summary
A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.