Sigma-Delta Frequency Synthesizer Dithering for Spur Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation methods using multiple oscillators or phase-locked loops are complex, inefficient, and incur high power consumption, size, and cost, particularly due to the difficulty in integrating capacitive loop filters within small areas and the noise reduction techniques that raise the noise floor.
Innovation Solution
A method and apparatus utilizing sigma-delta modulation to generate clock signals by combining dither and input signals, with interpolative dividers and phase interpolators, to produce multiple clock frequencies without separate phase-locked loops or oscillators, reducing digital spurs and phase noise through fractional division and phase adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple oscillators or phase-locked loops are used to synthesize multiple clock frequencies, then frequency generation capability is improved, but device complexity and area increase due to capacitive loop filters
Solution Approach 1:
The patent combines multiple clock generation functions into a single phase-locked loop by using a programmable frequency divider that can be configured to divide by different integer values. This eliminates the need for multiple separate oscillators and loop filters, reducing device complexity while maintaining the ability to generate multiple clock frequencies.
Solution Approach 2:
The frequency divider is designed to perform multiple functions: it can divide by programmable integer values to generate different clock frequencies, and it works in conjunction with a fixed capacitor to provide filtering for all frequency outputs. This universal approach allows one component to replace what would traditionally require multiple specialized components.
2Reliability
If capacitive loop filters are used in each phase-locked loop to filter out noise, then phase noise is reduced, but integration difficulty and area increase
Solution Approach 1:
The patent merges the filtering function into a shared resource by using a single fixed capacitor that works with the programmable frequency divider. This shared capacitor serves all frequency outputs, eliminating the need for multiple separate capacitive loop filters and making integration much easier while maintaining noise filtering performance.
3Reliability
If different techniques are employed to reduce phase noise, then phase noise is reduced, but power consumption and complexity increase
Solution Approach 1:
The system uses the existing frequency division operation to achieve noise reduction without requiring additional active filtering components or complex noise cancellation circuits. The programmable divider naturally provides frequency synthesis with inherent noise filtering, reducing power consumption compared to techniques that require additional active components.
Data Source
AI summary
A method includes operating on a sigma-delta modulated signal to reduce a dither signal component in one of a first signal and a second signal, the first signal being an integer portion corresponding to a digital frequency ratio and the second signal corresponding to a fractional portion of the digital frequency ratio. In at least one embodiment of the method, the operation is performed digitally in a frequency synthesizer.