Sigma-Delta Time-to-Digital Conversion for Calibration-Free PLLs
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Solution Overview
Problem
Existing time-to-digital converters face limitations in accuracy due to propagation time constraints and require calibration, especially when integrated into all-digital phase-locked loops, necessitating additional processing and normalization.
Innovation Solution
A sigma-delta type time-to-digital converter design that integrates pulses and implements sigma-delta negative feedback, eliminating the need for calibration and normalization, and operates within the dynamic range of the converter, using a multi-stage noise shaping architecture to improve signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flash time-to-digital converter using a delay line is used, then time period conversion is achieved, but measurement accuracy is limited by propagation time and calibration is required
Solution Approach 1:
The patent implements a sigma-delta feedback mechanism where the quantized output is fed back through an integrator to correct measurement errors. The feedback loop continuously adjusts the measurement by comparing the actual time interval with the expected value, eliminating the need for manual calibration while improving accuracy.
Solution Approach 2:
The patent changes the operating parameters by using multiple integration cycles and dynamic range adjustment. Instead of a single fixed-delay measurement, the system performs multiple integrations with varying time constants, allowing adaptive measurement that maintains accuracy across different time scales without requiring calibration.
2Adaptability or versatility
If a flash time-to-digital converter is implemented in an all digital phase-locked loop, then time conversion is achieved, but additional normalization processing is required
Solution Approach 1:
The patent merges the time-to-digital conversion function with the phase-locked loop operation by using the same clock signals and integrating the converter directly into the PLL feedback path. This combination eliminates the need for separate normalization processing, as the conversion is performed natively within the PLL's operational framework.
Solution Approach 2:
The patent creates a universal time measurement mechanism that operates within the phase-locked loop using its existing clock infrastructure. The converter uses the PLL's clock signals for both time measurement and loop operation, making the system multi-functional and eliminating the need for additional normalization circuitry.
3Measurement precision
If a delay line based converter is used, then time period conversion is achieved, but the converter requires calibration of propagation time in each stage
Solution Approach 1:
The patent implements a self-calibrating mechanism where the converter automatically adjusts its own measurement parameters using feedback from its own output. The system performs self-service calibration by comparing measurements across multiple integration cycles and automatically correcting for propagation time variations without external intervention.
Data Source
AI summary
The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).