Switched-Capacitor Sigma-Delta Modulator With Two-Phase Gain Calibration
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Solution Overview
Problem
Sigma-delta modulators face limitations in achieving high sampling rates with low gain error due to the need for four phases of sampling, which increases power consumption and reduces efficiency, while existing solutions require faster clocking and more complex components to maintain low gain error.
Innovation Solution
A sigma-delta modulator design that uses only two phases by sampling DAC and input signals in parallel on different capacitor pairs, with a rotation algorithm to cyclically assign capacitors to either signal or reference, ensuring accurate S/R gain and minimizing mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If four phases of sampling are used to achieve low gain error, then gain error is reduced to low ppm levels, but power consumption increases and throughput decreases
Solution Approach 1:
The capacitor array is segmented into multiple groups that can be independently assigned to different functions (signal sampling or reference sampling) in different phases. This segmentation allows the system to perform multiple sampling operations in parallel across different capacitor groups, reducing the total number of phases needed while maintaining accurate gain through the rotation algorithm that cycles capacitors through different assignment roles.
2Measurement precision
If four phases of sampling are used to achieve low gain error, then gain error is reduced to low ppm levels, but productivity decreases due to increased conversion time
Solution Approach 1:
The rotation algorithm ensures continuous useful action by cycling capacitor assignments through different roles (signal sampling, reference sampling) in a continuous rotating sequence. This allows the system to maintain accurate gain measurement across all capacitor groups over time while performing conversions at a higher rate, as multiple capacitor groups can be actively sampling in parallel during each phase rather than requiring sequential four-phase operation.
3Device complexity
If capacitors are assigned statically to signal or reference sampling, then device complexity is reduced, but gain error increases due to capacitor mismatch
Solution Approach 1:
The capacitor assignments are made dynamic through the rotation algorithm, which continuously cycles capacitors through different assignment roles (signal sampling, reference sampling, idle) in a predetermined rotating sequence. This dynamic reassignment allows each capacitor to participate in both signal and reference sampling over time, averaging out mismatch errors and achieving low gain error without requiring complex individual capacitor matching or calibration circuits.
4Productivity
If faster clocking is used to increase throughput, then productivity increases, but power consumption increases and gain error may worsen
Solution Approach 1:
The system merges multiple sampling operations into parallel execution by having multiple capacitor groups simultaneously perform signal sampling and reference sampling in the same phase. This merging allows the system to achieve high throughput through parallel processing without requiring faster clocking, thereby avoiding the increased power consumption and potential gain error that would result from operating at higher frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, doubles throughput, and maintains low gain error at parts-per-million levels without additional sampling time, enabling continuous gain error cancellation within the conversion process.
Implementation Method 1
A two-phase sampling and transfer algorithm is used wherein a plurality of capacitor pairs are used to sample and transfer in parallel the DAC and input signals
Implementation Method 2
a plurality of switches to couple any pair of capacitors from said plurality of capacitor pairs selectively to an input signal or a reference signal
Data Source
AI summary
A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.