Variable-Clock Sigma-Delta Modulator for Lower Output Rates
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Solution Overview
Problem
Sigma-delta modulators have high output rates due to over-sampling, which reduces efficiency and limits their applications, with existing methods either being unsuitable for multi-bit applications or introducing noise.
Innovation Solution
A sigma-delta modulator with an adder, filter, quantizer, and clock rate controller that adjusts the frequency of the clock signal based on the amplitude of the input signal, allowing for variable output rates without introducing additional noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If over-sampling is used in sigma-delta modulator, then noise suppression capability is improved, but output rate increases and efficiency decreases
Solution Approach 1:
The patent applies dynamics by making the sampling rate variable rather than fixed. The sampling rate controller dynamically adjusts the sampling rate based on the amplitude of the input signal, allowing the system to optimize between noise suppression and output rate efficiency in real-time conditions
Solution Approach 2:
The patent changes the parameter of sampling rate from a constant value to a variable value that depends on input signal characteristics. By adjusting the sampling rate parameter according to signal amplitude, the system achieves both noise suppression when needed and efficiency when possible
2Productivity
If sampling rate is reduced to improve efficiency, then productivity is improved, but noise suppression capability deteriorates
Solution Approach 1:
The system changes the sampling rate parameter dynamically based on input signal amplitude. When efficiency is prioritized, the sampling rate is reduced; when noise suppression is needed, the sampling rate is increased, achieving both goals at different times
Solution Approach 2:
The system transitions from static over-sampling to dynamic adaptive sampling. The sampling rate controller enables the system to respond to changing signal conditions, adjusting the sampling rate to maintain noise suppression only when necessary while improving overall efficiency
3Productivity
If PDM-to-PWM conversion is used to reduce output rate, then productivity is improved, but measurement precision deteriorates due to extra noise
Solution Approach 1:
The patent extracts and removes the problematic PDM-to-PWM conversion step from the system. Instead of using this conversion method that introduces noise, the invention directly controls the sampling rate at the quantizer stage, avoiding the introduction of extra noise while still achieving output rate reduction
Data Source
AI summary
A sigma-delta modulator includes an adder, a filter, a quantizer, and a clock rate controller. The adder receives an input signal and an output signal to generate a summation signal. The filter is coupled to the adder and filters the summation signal to generate a filtered signal. The quantizer is coupled to the filter as well as the adder and quantizes the filtered signal to generate the output signal according to a first clock signal. The clock rate controller is coupled to the quantizer and generates the first clock signal, wherein a frequency of the first clock signal is variable.